Modeling the effect of technology trends on the soft error rate of combinational logic
Modeling the effect of technology trends on the soft error rate of combinational logic
复制标题
DOI：
10.1109/dsn.2002.1028924
复制
发表时间：
2002-06
期刊：
影响因子：
--
通讯作者：
Premkishore Shivakumar;M. Kistler;S. Keckler;D. Burger;L. Alvisi
中科院分区：
文献类型：
--
作者：
Premkishore Shivakumar;M. Kistler;S. Keckler;D. Burger;L. Alvisi
本文研究了技术规模和微架构趋势对CMOS存储和逻辑电路中软错误率的影响。我们描述并验证了一个端到端模型，该模型使我们能够计算现有和未来微处理器风格设计的软错误率（SER）。该模型捕获了抑制组合逻辑软误差的两种重要掩蔽现象——电掩蔽和锁紧窗掩蔽。我们量化了SRAM单元、锁存器和逻辑电路中由于高能中子而产生的SER，其特征尺寸从600 nm到50 nm，时钟周期从16到6扇出4逆变器延迟。我们的模型预测，从1992年到2011年，逻辑电路的每个芯片的SER将增加9个数量级，届时将与未受保护的存储元件的每个芯片的SER相当。我们的研究结果强调，计算机系统设计者必须在未来的设计中解决逻辑电路软错误的风险。
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latching-window masking, which inhibit soft errors in combinational logic. We quantify the SER due to high-energy neutrons in SRAM cells, latches, and logic circuits for feature sizes from 600 nm to 50 nm and clock periods from 16 to 6 fan-out-of-4 inverter delays. Our model predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes that computer system designers must address the risks of soft errors in logic circuits for future designs.