A BISR Architecture for Embedded Memories
A BISR Architecture for Embedded Memories
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嵌入式存储器的 BISR 架构
DOI：
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发表时间：
2008
期刊：
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通讯作者：
N. Moschopoulos
中科院分区：
文献类型：
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作者：
K. Pekmestzi;N. Axelos;I. Sideris;N. Moschopoulos
本文提出了一种嵌入式存储器的BISR结构。提出的方案利用多个银行缓存式存储器进行修复。统计分析用于最小化实现非常高的故障覆盖率所需的总资源。仿真结果表明，即使在高缺陷密度的情况下，所提出的BISR方案也具有高效率和低面积开销的特点。在4mbit内存和每个IC平均1024个内存缺陷的情况下，100%和90%以上的修复率分别需要不到2%和1%的内存开销。
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities. On a 4 Mbit memory and an average number of 1024 memory defects per IC, a repair ratio of 100% and over 90% require less than 2% and 1% memory overhead respectively.