Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry
Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry
复制标题
降低数字电路中基底噪声的异步方法的实验表征和分析
DOI：
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发表时间：
2012
影响因子：
2.8
通讯作者：
T. Fiez
中科院分区：
文献类型：
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作者：
Jim Le;Christopher Hanken;Martin Held;M. Hagedorn;K. Mayaram;T. Fiez
延迟不敏感的异步电路在由于局部开关引起的衬底噪声方面提供了显著的优点。根据测试结果，分析了空常规逻辑（NCL）和传统时钟布尔逻辑（CBL）的衬底噪声差异。采用TSMC 0.25 μm工艺制造的测试芯片表明，与等效同步设计相比，采用NCL实现的伪随机数发生器产生的衬底噪声降低了23 dB。在较大规模的数字电路中，异步8051处理器提供的衬底噪声比同步处理器的衬底噪声提高了近10 dB。以三角积分调制器（DSM）为例，研究了这种衬底噪声对模拟电路的影响。二阶DSM的信噪比性能不受来自NCL 8051处理器的衬底噪声的影响，而当CBL 8051处理器被时钟控制在接近DSM采样频率的整数倍时，其经历高达15 dB的降级。
Delay insensitive asynchronous circuitry provides significant advantages with respect to substrate noise due to localized switching. The differences between the substrate noise from NULL convention logic (NCL) and traditional clocked Boolean logic (CBL) are described and analyzed based on measured results. A test chip fabricated in the TSMC 0.25 μm process shows that a pseudo-random number generator implemented with NCL generates 23 dB less substrate noise compared to the equivalent synchronous design. In a larger scale digital circuit, the substrate noise improvement offered by an asynchronous 8051 processor over its synchronous counterpart was nearly 10 dB. The effect of this substrate noise on an analog circuit was explored with a delta-sigma modulator (DSM) example. The signal-to-noise ratio performance of a second order DSM was not affected by the substrate noise from the NCL 8051 processor while it experiences up to 15 dB degradation when the CBL 8051 processor is clocked near integer multiples of the DSM sampling frequency.