Unleashing the potential of MLC STT-RAM caches
Unleashing the potential of MLC STT-RAM caches
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DOI：
10.1109/iccad.2013.6691153
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发表时间：
2013-11
期刊：
影响因子：
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通讯作者：
Xiuyuan Bi;Mengjie Mao;Danghui Wang;Hai Helen Li
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文献类型：
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作者：
Xiuyuan Bi;Mengjie Mao;Danghui Wang;Hai Helen Li
在本文中，我们研究了在嵌入式系统和微处理器的高速缓存设计中使用多级细胞（MLC）自旋转移扭矩RAM（STT-RAM）。与单级单元格（SLC）设计相比，MLC STT-RAM缓存有望提供更高的密度和更快的系统性能。但是，细胞设计会限制，例如切换电流需求和写操作中的不对称性，严重限制了常规MLC STT-RAM的密度益处。现有的MLC STT-RAM缓存体系结构中的两步读/写入访问和僵化的数据映射策略甚至可能导致系统性能退化。为了释放MLC STT-RAM缓存的真正潜力，我们提出了跨层溶液。首先，我们将反磁连接隧道（MTJ）引入MLC单元格设计，该设计提供了更平衡的设备和设计权衡，并使2倍存储密度比SLC提供了2倍的存储密度。在体系结构层面，我们提出了一种单元格映射方法，将缓存线分为快速，缓慢的区域以及数据迁移策略，以将经常使用的数据分配给快速区域。此外，使用应用程序感知的速度增强模式可用于自适应折衷的缓存能力和速度，满足各种应用程序的不同要求。仿真结果表明，与常规MLC STT-RAM相比，提出的技术可以将系统性能提高10.3％，并将缓存的能源消耗降低26.0％。
In this paper, we study the use of multi-level cell (MLC) spin-transfer torque RAM (STT-RAM) in cache design of embedded systems and microprocessors. Compared to the single level cell (SLC) design, a MLC STT-RAM cache is expected to offer higher density and faster system performance. However, the cell design constrains, such as the switching current requirement and asymmetry in write operations, severely limit the density benefit of the conventional MLC STT-RAM. The two-step read/write accesses and inflexible data mapping strategy in the existing MLC STT-RAM cache architecture may even result in system performance degradation. To unleash the real potential of MLC STT-RAM cache, we propose a cross-layer solution. First, we introduce the reverse magnetic junction tunneling (MTJ) into MLC cell design, which offers a more balanced device and design tradeoff and enables 2x storage density than SLC. At architectural level, we propose a cell split mapping method to divide cache lines into fast and slow regions and data migration policies to allocate the frequently-used data to fast regions. Furthermore, an application-aware speed enhancement mode is utilized to adaptively tradeoff cache capacity and speed, satisfying different requirements of various applications. Simulation results show that the proposed techniques can improve the system performance by 10.3% and reduce the energy consumption on cache by 26.0% compared with conventional MLC STT-RAM.