A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications
A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications
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DOI：
10.1109/tcsi.2014.2312479
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发表时间：
2014-04
期刊：
影响因子：
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通讯作者：
C. Cheng;Jeng-Da Yang;Huang-Chang Lee;Chia-Hsiang Yang;Yeong-Luh Ueng
中科院分区：
文献类型：
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作者：
C. Cheng;Jeng-Da Yang;Huang-Chang Lee;Chia-Hsiang Yang;Yeong-Luh Ueng
提出了一种适用于低密度奇偶校验(LDPC)码的归一化概率最小和算法，该算法使用概率次最小值代替真正的次最小值，以便于完全并行译码实现。每个校验节点单元(CNU)中的比较器通过基于树形和蝶形混合网络的互连网络连接，从而可以有效地实现可变节点单元(VNU)和CNU之间的路由和消息传递。为了进一步降低硬件复杂度，归一化操作在VNU中实现，而不是在CNU中。为了防止低信噪比和高信噪比区域的不必要能量消耗，提出了一种提前终止方案。通过使用90 nm工艺实现(2048,1723)LDPC译码，验证了所提技术的有效性。版图后仿真结果表明，该解码器在199.6 MHz时的吞吐量为45.42Gbps，在误码性能相近或更好的情况下，获得了同类工作中最高的吞吐量和吞吐面积比。
This paper presents a normalized probabilistic min-sum algorithm for low-density parity-check (LDPC) codes, where a probabilistic second minimum value, instead of the true second minimum value, is used to facilitate fully parallel decoder realization. The comparators in each check-node unit (CNU) are connected through an interconnect network based on a mix of tree and butterfly networks such that the routing and message passing between the variable-node units (VNUs) and CNUs can be efficiently realized. In order to further reduce the hardware complexity, the normalization operation is realized in the VNU rather than in the CNU. An early termination scheme is proposed in order to prevent unnecessary energy dissipation for both low and high signal-to-noise-ratio regions. The proposed techniques are demonstrated by implementing a (2048, 1723) LDPC decoder using a 90 nm CMOS process. Post-layout simulation results show that the decoder supports a throughput of 45.42 Gbps at 199.6 MHz , achieving the highest throughput and throughput-to-area ratio among comparable works based on a similar or better error performance.