A 3D IC BIST for pre-bond test of TSVs using ring oscillators
A 3D IC BIST for pre-bond test of TSVs using ring oscillators
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使用环形振荡器进行 TSV 预键合测试的 3D IC BIST
DOI：
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发表时间：
2013
期刊：
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通讯作者：
G. D. Natale
中科院分区：
文献类型：
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作者：
Yassine Fkih;P. Vivet;B. Rouzeyre;M. Flottes;G. D. Natale
基于硅通孔（TSV）的3D叠层集成电路具有高性能和小尺寸等优点。然而，这些电路存在许多测试问题，特别是对于TSV。在本文中，我们提出了一种新的内建自测试（BIST）结构的预键合测试的TSV在3D堆叠集成电路。其主要思想是测量TSV电容的变化，以检测有缺陷的TSV。BIST架构基于环形振荡器，其频率取决于TSV电容。所提出的BIST集成在JTAG标准中。本文给出了采用65 nm CMOS工艺，包括10 μm直径TSV中间工艺的TSV环形振荡器结构的SPICE仿真结果和逻辑综合结果。由于局部工艺的变化，所提出的测试架构是有限的准确性，它只检测大的电容性故障的TSV。
3D stacked integrated circuits based on Through Silicon Vias (TSV) are promising with their high performances and small form factor. However, these circuits present many test issues, especially for TSVs. In this paper we propose a novel Built-In-Self-Test (BIST) architecture for pre-bond testing of TSVs in 3D stacked integrated circuits. The main idea is to measure the variation of TSVs capacitances in order to detect defective TSVs. The BIST architecture is based on ring oscillators, frequencies of which depend on TSVs capacitances. The proposed BIST is integrated within the JTAG standard. This paper presents spice simulation results and logic synthesis results of the proposed TSV ring oscillator structure using a 65 nm CMOS technology, including 10 μm diameter TSV middle technology. Due to local process variations, the proposed test architecture is limited in accuracy; it detects only large capacitive faults on TSVs.