The VeloPix ASIC
The VeloPix ASIC
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VeloPix ASIC
DOI：
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
V. Gromov
中科院分区：
文献类型：
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作者：
T. Poikela;R. Ballabriga;J. Buytaert;X. Llopart;W. Wong;M. Campbell;K. Wyllie;M. Beuzekom;J. Schipper;Sandeep Miryala;V. Gromov
VeloPix是一款130纳米CMOS技术芯片，具有数据驱动和零抑制读出功能，将被用作LHCb顶点定位器（VELO）升级的混合像素系统的读出芯片。这次升级计划在LHC Run-3中进行，将使实验能够在无触发模式下以40mhz的频率读取，事件选择在CPU场中执行。最高占用asic的速率将超过900毫秒/秒，距离LHC光束最近的像素为5.1毫米。本文将介绍VeloPix ASIC以及没有传感器的第一次测试结果。
VeloPix, a 130 nm CMOS technology chip with data driven and zero suppressed readout, will be used as a readout chip for the hybrid pixel system of the LHCb Vertex Locator (VELO) upgrade. The upgrade, scheduled for LHC Run-3, will enable the experiment to be read out at 40 MHz in trigger-less mode, with event selection being performed in the CPU farm. The highest occupancy ASICs will experience rates of more than 900 Mhits/s, and the closest pixels are 5.1 mm from the LHC beams. This paper will present the VeloPix ASIC along with the first test results without a sensor.