A Capacitance-Minimized, Doubly Grounded Transformer less Photovoltaic Inverter With Inherent Active-Power Decoupling
A Capacitance-Minimized, Doubly Grounded Transformer less Photovoltaic Inverter With Inherent Active-Power Decoupling
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DOI：
10.1109/tpel.2016.2606344
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发表时间：
2017-07
影响因子：
6.7
通讯作者：
Yinglai Xia;Jinia Roy;R. Ayyanar
中科院分区：
文献类型：
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作者：
Yinglai Xia;Jinia Roy;R. Ayyanar
无变压器光伏(PV)逆变器面临的两大挑战是共模泄漏电流的存在，以及与大多数单相变流器一样，需要可靠而紧凑的双线频电源解耦。在所提出的具有创新有功功率解耦方法的双接地逆变器拓扑中，同时解决了这两个问题。该拓扑允许PV负极端子直接连接到中性点，从而消除了电容耦合的共模接地电流。通过具有大电压摆幅的动态可变直流环节，可以最大限度地降低去耦电容要求，从而实现全薄膜电容器实施。此外，宽禁带器件的使用使转换器能够在更高的开关频率下运行，从而产生更小的磁元件。该拓扑仅使用四台交换机，有可能实现高功率密度解决方案。详细阐述了其工作原理、设计优化和控制方法，并与其他无变压器、有源解耦拓扑进行了比较。用45μF/1100V直流环节电容的SiCMOSFET研制了一台额定输入为400V，交流输出为240V，功率因数范围宽的3kVA，100/75 kHz单相硬件样机。样机的大量实验结果验证了所提出的拓扑结构的概念、设计和优越的性能。
Two major challenges in the transformerless photovoltaic (PV) inverters are the presence of common-mode leakage currents, and as in most single-phase converters the need for reliable and compact double-line-frequency power decoupling. In the proposed doubly grounded inverter topology with innovative active-power-decoupling approach, both of these issues are simultaneously addressed. The topology allows the PV negative terminal to be directly connected to the neutral, thereby eliminating the capacitive-coupled common-mode ground currents. The decoupling capacitance requirement is minimized by a dynamically variable dc-link with large voltage swing, allowing an all-film-capacitor implementation. Furthermore, the use of wide bandgap devices enables the converter operation at higher switching frequency, resulting in smaller magnetic components. The topology uses only four switches and potentially enables a high power density solution. The operating principles, design and optimization, and control methods are explained in detail, and compared with other transformer-less, active-decoupling topologies. A 3 kVA, 100/75 kHz single-phase hardware prototype at 400 V dc nominal input and 240 V ac output with a wide range of power factor has been developed using SiC MOSFETs with only 45 μF/1100 V dc-link capacitance. Extensive experimental results from the prototype are presented to validate the concept, design, and superior performance of the proposed topology.