An Efficient Architecture Implemented to Reduce Area in VLSI Adders
An Efficient Architecture Implemented to Reduce Area in VLSI Adders
复制标题
一种用于减少 VLSI 加法器面积的高效架构
DOI：
--
复制
发表时间：
2017
期刊：
影响因子：
--
通讯作者：
Sethu Selvi
中科院分区：
文献类型：
--
作者：
K. Kaarthik;S. Pradeep;Sethu Selvi
加法器在算术逻辑单元中扮演着重要的角色。它通常用于IC芯片的工作。在IC芯片的组装中，利用加法器的实现，通过减少入口数量来减少面积。如果门的数量减少，那么功耗也会随之减少，同时准备速度也会因延迟的减少而增加。这些减小面积、功耗、延迟和增加速度的过程将在低功耗 VLSI 设计准备中获得。在本文中，我们考虑并行前缀加法器（PPA）。并行前缀加法器用于加速二进制加法过程。这项工作包括将不同的并行前缀加法器关联起来，以获得一个加法器，该加法器可以在有限的容量内获得输出，从而以较少的功率和面积来集中时间。他们的产量被模仿，并给出了一个比较表，以证明首选加法器可以获得更好的结果。
The Adder assumes an imperative part in Arithmetic Logic Unit. It is generally utilized in working of an IC chip. In the assembling of IC chip the Implementation of Adder is utilized to Reduce the Area by decreasing the Number of entryways. In the event that the quantity of doors gets decreased then Power Consumption is likewise gets lessened all the while the preparing pace will be Increased by diminishment in Delay. These procedure of diminished Area, Power Consumption, Delay and Increased Speed will be acquired in Low Power VLSI Design prepare. In this Paper we consider the Parallel Prefix Adder (PPA) . The Parallel Prefix Adders are utilized to Speed up the Binary Addition Process. The work includes the correlation of different parallel prefix adder to acquire an Adder which can ready to get the Output in limited capacity to focus time with utilization of less Power and Area. Their yields are mimicked and a Comparison table have been given to Justify that the Preferred adder can get better Result.