ANALYSIS OF TEMPERATURE-DEPENDENT RESIDUAL STRESS GRADIENTS IN CMOS MICROMACHINED STRUCTURES
ANALYSIS OF TEMPERATURE-DEPENDENT RESIDUAL STRESS GRADIENTS IN CMOS MICROMACHINED STRUCTURES
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CMOS微机械结构中随温度变化的残余应力梯度分析
DOI：
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发表时间：
1999
期刊：
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通讯作者：
G. Fedder
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文献类型：
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作者：
H. Lakdawala;G. Fedder
本文提出了一种分析多层CMOS微结构中残余应力梯度引起的结构旋度随温度变化的方法。利用有限元分析和实验验证的解析方程作为有限元技术预测任意装置残余应力相关旋度的基础。提出了一种基于测量叶尖挠度随温度变化的参数提取方法来提取仿真参数。简单的光束测试结构组成的所有金属-电介质组合可能在惠普3-meta 1.0。对5μm n- well CMOS工艺进行了实验表征。该信息用于获得梁无垂直位移且每层应力为零的特征温度。利用叶尖挠度随温度的变化率提取了每一层的热膨胀系数。在有限元分析中引入特征温度和TCE来预测结构的温度旋度。这种预测技术已经在一个螺旋匹配的CMOS加速度计上得到了验证。CMOS表面微加工技术通过传统的CMOS工艺，以低成本将电路与机械结构集成在一起。它提供了在微结构中放置多个隔离导体的能力，用于新型电容传感。由金属层和介电层交织组成的多层结构材料表现出诱发结构卷曲的残余应力梯度。由于各层TCE的差异，各层的应力是温度的函数。这种结构卷曲的变化导致横向电容传感器灵敏度的变化，因为相邻电极之间的耦合面积发生了变化。卷发匹配技术已经被用来最小化这些变化的影响。为了设计和验证结构的匹配旋度，必须预测温度对结构旋度的影响。对CMOS微加工光束的温度相关旋度的分析扩展了Timoshenko对热双晶[2][3]的处理，并得到了描述光束尖端挠度随温度变化的方程。每一层的残余应力效应用梁完全平坦的特征温度来表示。每种材料的TCE值是由测量到的尖端挠度随温度的变化率实验提取的。利用材料性能和特征温度进行有限元分析，预测任意CMOS表面微加工结构的卷曲。本文所描述的器件是在卡耐基梅隆大学开发的高纵横比CMOS微加工工艺中制造的。工艺流程如图1所示，可以在标准的0.5μm 3金属CMOS工艺中制造微机械结构。传统的CMOS工艺之后是用CHF3和O2进行各向异性反应蚀刻（RIE），以蚀刻掉未被任何金属层覆盖的氧化物，从而产生高纵横比的垂直侧壁。各向同性RIE（使用SF6和O2）然后去除底层硅，从而释放微观结构。热多晶圆分析CMOS微机械结构可以设计为任何金属层作为顶部金属掩膜，从而为器件的每个元件的设计提供了多种选择。图1：标准CMOS微加工结构的工艺示意图。(一)
In this paper, we present a technique to analyze variation of structural curl with temperature due to residual stress gradients in multilayer CMOS microstructures. Analytic equations verified by finite element analysis (FEA) and experiment are used as a basis for a FEA technique to predict residual stress dependent curl in an arbitrary device. A parameter extraction method based on measurement of tip deflection with temperature is proposed to extract the simulation parameters. Simple beam test structures composed of all metal-dielectric combinations possible in the Hewlett Packard 3-meta l 0 .5μm n-wel l CMOS process are experimentally characterized. This information is used to obtain the characteristic temperature at which the beam has no vertical displacement and the stresses in each layer is zero. The thermal coefficient of expansion (TCE) for each layer is extracted using the rate of change of tip deflection with temperature. The characteristic temperature and TCE are inserted in FEA for prediction of structural curl with temperature. This predictive technique has been demonstrated for a curl-matched CMOS accelerometer. INTRODUCTION CMOS surface-micromachining technology through conventional CMOS processing integrates circuits with mechanical structures at low cost. It provides an ability to place multiple isolated conductors in microstructures for novel capacitive sensing. The multilayer structural material, composed of metal layers with interleaved dielectric layers, exhibits residual stress gradients that induce structural curling. Stress in each layer is a function of temperature due to the differences in the TCE of the layers. This variation of structural curling leads to variation of sensitivity of lateral capacitive sensors, as the coupling area between adjacent electrodes changes. Curl-matching techniques have been used to minimize the effect of these variations[1]. To design and verify matched curl in structures it is imperative to predict structural curl variation due to temperature. The analysis of temperature-dependent curl for CMOS micromachined beams extends Timoshenko’s treatment of thermal bimorphs[2][3] and results in equations describing the beam tip deflection with temperature. The residual stress effects in each layer are represented by a characteristic temperature at which the beam is completely flat. The TCE values for each material are extracted experimentally from the measured rate of change of tip deflection with temperature. The material properties and the characteristic temperature are used in a FEA to predict curling of arbitrary CMOS surface-micromachined structures. CMOS MICROMACHINING PROCESS The devices described in this paper have been fabricated in the high-aspect-ratio CMOS micromachining process developed at Carnegie Mellon University [4]. The process flow, shown in Figure 1, enables fabrication of micromachined structures in a standard 0.5μm 3-metal CMOS process. The conventional CMOS process is followed by an anisotropic reactive-ion etch (RIE) with CHF3 and O2 to etch away oxide not covered by any of the metal layers, resulting in high aspect ratio vertical sidewalls. An isotropic RIE (using SF6 and O2) then removes the underlying silicon, thus releasing the microstructure. THERMAL MULTIMORPH ANALYSIS A CMOS micromachined structure can be designed with any of the metal layers as the top metal mask leading to numerous choices for the design of each element of a device. Figure 1: Schematic of the process for micromachined structures in standard CMOS. (a)