Optimal sleep transistor synthesis under timing and area constraints
Optimal sleep transistor synthesis under timing and area constraints
复制标题
时序和面积限制下的最佳睡眠晶体管综合
DOI：
10.1145/1366110.1366155
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
M. Poncino
中科院分区：
文献类型：
--
作者：
A. Sathanur;A. Pullini;L. Benini;A. Macii;E. Macii;M. Poncino
降低纳米cmos设计的漏功率已经引起了学术界和工业界的极大兴趣。文献中提出了许多降低泄漏功率的技术，其中一个突出的技术是使用睡眠晶体管作为功率门控元件，在电路处于待机模式时切断亚阈值泄漏电流。虽然休眠晶体管的插入是非常有效的切断漏电，它也招致时间，面积和路由开销。由于大多数休眠晶体管插入方法都是在布局插入后进行的，因此应注意使对原始布局的扰动最小。必须避免过度设计休眠晶体管单元和次优休眠晶体管放置，以实现最终设计闭合。由于休眠晶体管的面积在这方面起着重要而突出的作用，因此需要在面积限制下优化休眠晶体管的尺寸和合成技术。在本文中，我们首先提供了一种在给定面积约束下的最佳休眠晶体管合成方法。然后，我们将我们的技术应用于[13]中提出的一般时序和面积约束驱动的基于行的功率门控方法，并展示了如何设计具有时序和面积约束的最佳低漏设计。
Leakage power reduction in nano-CMOS designs has gained tremendous interest both in academia and industry. Many techniques have been proposed in the literature for leakage power reduction and one of the prominent techniques for leakage power reduction is the use of sleep transistors as power-gating elements to cut-off sub-threshold leakage current in circuits when they are in stand-by mode. Although sleep transistor insertion is very effective in cutting-off leakage, it also incurs timing, area and routing overhead. Since most of the sleep transistor insertion methodologies do post layout insertion, care should be taken such that there is minimal perturbation of the original layout. Over design of sleep transistors cells and sub-optimal sleep transistor placement must be avoided to achieve final design closure. Since the sleep transistor area plays an important and prominent role in this aspect, it necessitates for optimal sleep transistor sizing and synthesis technique under area constraints. In this paper, we first provide a methodology for optimal sleep transistor synthesis under given area constraints. We then apply our technique to the general timing and area constraint driven row-based power-gating methodology proposed in [13] and show how optimal low leakage designs with constraints on timing and area can be designed.