Automatic architecture refinement techniques for customizing processing elements
Automatic architecture refinement techniques for customizing processing elements
复制标题
用于定制处理元件的自动架构细化技术
DOI：
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发表时间：
2008
期刊：
影响因子：
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通讯作者：
D. Gajski
中科院分区：
文献类型：
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作者：
B. Gorjiara;D. Gajski
在本文中，我们提出了一种使用静态调度的基于纳码的架构来设计高性能节能处理元件（PE）的方法。我们的方法基于自下而上的细化/修剪技术，该技术可以优化给定的数据路径，无论它是手动设计的还是自动生成的。优化还可以保留设计者指定的部分网表，因此允许重复使用设计工作，并可以实现可预测的收敛。在本文中，我们表明，修剪典型通用数据路径的未使用和未充分利用的资源可以平均节省 30-40% 的能源，而不会造成任何性能损失。然而，通用架构通常会牺牲并行性来使设计可实现。通过我们的修剪方法，我们可以拥有一个不用于实现且具有更多并行性的基础架构，然后应用细化以使其可实现。对于我们的基准测试，与两种通用架构（即 4 个问题 VLIW 和 DLX）相比，我们分别实现了高达 1.8 倍（平均 25%）和 2.6 倍（平均 40%）的性能改进。此外，与精简后的通用架构相比，能耗降低高达 5 倍（平均 2 倍）。
In this paper, we propose an approach for designing high- performance energy-efficient processing elements (PEs) using statically- scheduled nanocode-based architectures. Our approach is based on bottom-up refinement/trimming techniques that optimize a given datapath irrespective of whether it was designed manually or generated automatically. The optimizations can also preserve parts of the netlist specified by the designers, and hence, allow reuse of design efforts and can lead to predictable convergence. In this paper, we show that trimming unused and underutilized resources of typical general-purpose datapaths can lead to 30-40% average energy savings, without any performance loss. However, general-purpose architectures often compromise parallelism to make the design implementable. With our trimming approach, we can afford to have a base architecture that is not intended for implementation and has more parallelism, and then apply refinement to make it implementable. For our benchmarks, we achieved up to 1.8 times (avg. 25%) and 2.6 times (avg. 40%) performance improvement, compared to two general-purpose architectures (i.e. a 4- issue VLIW and a DLX), respectively. Additionally, the energy consumption is reduced by up to 5 times (avg. 2 times) compared to the trimmed general-purpose architectures.