Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization
Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization
复制标题
CMOL 电路的缺陷容错映射目标延迟优化
DOI：
10.1007/s11390-021-0904-0
复制
发表时间：
2021
影响因子：
0.7
通讯作者：
Zhu-Fei Chu
中科院分区：
文献类型：
--
作者：
Xiao-Jing Zha;Yin-Shui Xia;Shang-Luan Xie;Zhu-Fei Chu
鉴于在CMOS/纳米线/分子混合(CMOL)电路中存在大量的有缺陷的纳米器件，容错映射是在有缺陷的CMOL电路中实现正确逻辑操作的关键步骤。然而，通过容错策略来改善电路延迟的努力较少。分析了影响映射电路时延的因素，提出了一种基于路径树的时延优化容错映射方法。从逻辑域出发，提出了路径树的概念，并首先将逻辑电路划分为多棵路径树。然后，为关键路径树(附近)预先规划物理域中的映射区域。在映射过程中，制定了具体的映射模式和更新策略来映射路径树：根据输入排序映射输入；优先映射(近)关键路径树，而其他关键路径树以分层方式映射。最后，采用改进的禁忌搜索算法验证了该容错映射方法的有效性。在ISCAS基准上的实验结果表明，该方法可以将电路时延降低15.22%。
In view of the significant number of defective nanodevices in the Cmos/nanowire/MOLecular hybrid (CMOL) circuit, defect-tolerant mapping is an essential step to achieve correct logic operations in defective CMOL circuits. However, less effort has been made to improve circuit delay by defect-tolerant strategies. In this paper, the factors affecting the delay of mapped circuits are analyzed, and the path-tree based defect-tolerant mapping method for the delay optimization is proposed. From the logic-domain, the terminology of the path tree is presented, and the logic circuit is first partitioned into multiple path trees. Then, the mapping areas in the physic-domain are pre-planned for (near) critical path trees. During the mapping process, the specific mapping modes and an updating strategy are formulated to map the path trees: inputs are mapped based on input sorting; (near) critical path trees are mapped with priority, while the others are mapped in a hierarchical way. Finally, an improved tabu search algorithm is employed to verify the validity of the proposed defect-tolerant mapping method. Experimental evaluations on the ISCAS benchmarks show that the proposed method can reduce circuit delay by 15.22%.