SIFO: Secure Computational Infrastructure Using FPGA Overlays

SIFO: Secure Computational Infrastructure Using FPGA Overlays
复制标题

SIFO:使用 FPGA 覆盖的安全计算基础设施

DOI:
10.1155/2019/1439763
复制
发表时间:
2019
影响因子:
4.3
通讯作者:
Leeser, Miriam
Leeser, Miriam
中科院分区:
--
文献类型:
--
作者:
Fang, Xin;Ioannidis, Stratis;Leeser, Miriam

文献摘要

相似文献

安全功能评估(SFE)最近由于个人数据的大量收集和挖掘而受到关注,但由于其巨大的计算成本仍然不切实际。 Garbled Circuits (GC) 是一种用于实现 SFE 的协议,它可以评估任何可以表示为布尔电路的函数并获得结果,同时保持各方输入的私密性。最近的进展导致了用于各种不同任务的软件中乱码电路实现的激增。然而,这些实现效率低下,因此 GC 没有被广泛使用,特别是对于大型问题。本研究使用具有 FPGA 的异构计算平台来研究、实施和评估安全计算生成。我们设计并实现了 SIFO:使用 FPGA 覆盖的安全计算基础设施。与传统的FPGA设计不同,它采用了粗粒度的覆盖架构,支持将太大而无法映射到单个FPGA的SFE问题映射。提供的主机工具包括 SFE 问题生成器、解析器和自动主机代码生成。我们的设计允许重新利用 FPGA 来评估不同的 SFE 任务,而无需重新编程,并充分探索任何 GC 问题的并行性。与现有软件平台相比,我们的系统显示出一个数量级的加速。
Secure Function Evaluation (SFE) has received recent attention due to the massive collection and mining of personal data, but remains impractical due to its large computational cost. Garbled Circuits (GC) is a protocol for implementing SFE which can evaluate any function that can be expressed as a Boolean circuit and obtain the result while keeping each party’s input private. Recent advances have led to a surge of garbled circuit implementations in software for a variety of different tasks. However, these implementations are inefficient, and therefore GC is not widely used, especially for large problems. This research investigates, implements, and evaluates secure computation generation using a heterogeneous computing platform featuring FPGAs. We have designed and implemented SIFO: secure computational infrastructure using FPGA overlays. Unlike traditional FPGA design, a coarse‐grained overlay architecture is adopted which supports mapping SFE problems that are too large to map to a single FPGA. Host tools provided include SFE problem generator, parser, and automatic host code generation. Our design allows repurposing an FPGA to evaluate different SFE tasks without the need for reprogramming and fully explores the parallelism for any GC problem. Our system demonstrates an order of magnitude speedup compared with an existing software platform.