Structured Placement with Topological Regularity Evaluation
Structured Placement with Topological Regularity Evaluation
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DOI：
10.2197/ipsjtsldm.2.222
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发表时间：
2007-01
期刊：
影响因子：
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通讯作者：
S. Nakatake
中科院分区：
文献类型：
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作者：
S. Nakatake
本文介绍了一种新的布图规划和块布局的概念，称为结构化布局。规则性是结构化布局的关键标准，因此布局可以超越约束驱动的方法。本文给出了从序列偶中提取的拓扑正则性。像数组和行这样的常规结构是在单个序列上定义的，单个序列是序列对的一种标准表示。我们从0（n）中的单个序列中提取规则结构，然后通过量化规则性作为目标函数来评估结构。此外，我们提出了一个新的模拟退火（SA）框架，称为双SA，在那里我们传达了一个建设性的功能，SA框架，使它达到一个平衡的大小对面积效率的常规结构的位置。在实验中，我们将我们的结构化布局模拟块设计，并揭示了明确的优势，我们的布局包含许多规则的结构，如行和阵列，而不增加芯片面积和导线长度，相比现有的布局。
This paper introduces a new concept of floorplanning and block placement, called structured placement. Regularity is a key criterion of structured placement so that placement can make progress beyond constraint-driven approaches. This paper formulates the topological regularity that is extractable from a sequence-pair. Regular structures like arrays and rows are defined on a single-sequence that is a kind of standard representation of a sequence-pair. We extract regular structures from a single-sequence in 0(n), and then evaluate the structures by quantifying the regularity as an objective function. Besides, we propose a new simulated annealing (SA) framework, called dual SA, where we convey a constructive feature to an SA framework, so that it attains a placement balancing the size of regular structures against the area efficiency. In experiments, we apply our structured placement to analog block designs, and reveal the definite advantage that our placements contain many regular structures such as rows and arrays without increasing the chip area and the wire length, compared to the existing placement.