Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits
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DOI：
10.1109/socc56010.2022.9908116
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发表时间：
2022-09
期刊：
影响因子：
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通讯作者：
Jun Shiomi;Shogo Terada;T. Ishihara;H. Onodera
中科院分区：
文献类型：
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作者：
Jun Shiomi;Shogo Terada;T. Ishihara;H. Onodera
本文提出了一种采用细粒度功率门控技术的标准单元存储结构，用于低压电路。考虑到在人工智能等许多应用中都会出现大量的零，功率门控技术被应用于只存储零的位单元。在描述了一种适合于细粒度功率门控的标准单元结构之后，本文提出了一种内置功率开关的存储单元结构。通过精细和动态地关闭仅存储零的锁存单元，可以减少泄漏能量，同时我们可以完全访问整个存储器数据。采用55纳米商用工艺技术的实验结果表明，泄漏能耗可降低33%。
This paper proposes a standard-cell memory structure with fine-grained power gating techniques for low voltage circuits. Focusing on the fact that a number of zeros appear in many applications such as artificial intelligence, power gating techniques are applied to bit cells storing zeroes only. After describing a standard-cell structure which is suitable for fine-grained power gating, this paper proposes a memory cell structure with a built-in power switch. By finely and dynamically powering off only the latch cells storing zeroes only, leakage energy can be reduced while we can fully access the entire memory data. Experimental results using a 55-nm commercial process technology show that up to 33% leakage energy consumption can be reduced.