Inorganic p-channel thin-film transistors using CuO nanoparticles
Inorganic p-channel thin-film transistors using CuO nanoparticles
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DOI：
10.1117/12.2500644
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发表时间：
2019-01
期刊：
影响因子：
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通讯作者：
Julia Reker;T. Meyers;F. Vidor;U. Hilleringmann
中科院分区：
文献类型：
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作者：
Julia Reker;T. Meyers;F. Vidor;U. Hilleringmann
本研究的重点是铜氧化物纳米粒子形成无机p沟道薄膜晶体管（TFT）的集成。所使用的CuO纳米颗粒的直径为25-55 nm，并分散在水基溶液中，提供了低成本和大规模集成工艺的机会。由于半导体必须承受的低化学和物理应力，使用倒置共面TFT架构实现了第一次调查。因此，将由50 nm铝接着7 nm钛组成的栅电极集成在Si/SiO2衬底上。作为栅极电介质，通过旋涂沉积高k有机-无机纳米复合材料，得到150- 180 nm的层厚度。对于漏极和源极，检查金和镍。对于这两种金属化的影响与自组装单层（2，3，4，5，6五氟苯硫酚，PFBT）的电极处理进行了研究。栅极金属化以及漏极/源极电极通过电子束蒸发，并通过光刻，然后分别通过湿法蚀刻工艺和剥离技术进行结构化。在最后一步中，通过刮刀法施加CuO纳米颗粒层，然后在环境条件下在对流烘箱中蒸发溶剂。集成过程中的最高温度为115°C，因此与玻璃和箔基材具有相容性。探讨了漏/源材料对电特性的影响以及电极处理的影响。此外，还分析了互补技术中的单TFT无机反相电路。
This study focuses on the integration of copper oxide nanoparticles forming inorganic p-channel thin-film transistors (TFTs). The used CuO nanoparticles have a diameter of 25-55 nm and are dispersed in a water-based solution providing the opportunity of low-cost and large-scale integration processes. First investigations were realized using an inverted coplanar TFT architecture due to the low chemical and physical stresses the semiconductor has to withstand. Therefore, a gate electrode consisting of 50 nm aluminum followed by 7 nm titanium was integrated on a Si/SiO2 substrate. As gate dielectric a high-k organic-inorganic nanocomposite was deposited by spin-coating resulting in a layer thickness of 150- 180 nm. For the drain and source electrodes gold and nickel were examined. For both metallizations the influence of an electrode treatment with a self-assembling monolayer (2,3,4,5,6 Pentafluorothiophenol, PFBT) was investigated. The gate metallization as well as the drain/source electrodes were evaporated via e-beam and structured by photolithography followed by wet-etching processes and lift-off technique, respectively. In the last step, the CuO nanoparticle layer was applied by doctor blade process followed by evaporating the solvent in a convection oven under ambient conditions. The maximum temperature during the integration process was 115°C so that a compatibility to glass and foil substrates is given. The influence of the drain/source material on the electrical characteristics was explored as well as the impact of the electrode treatment. Besides single TFTs inorganic inverter circuits in complementary technique were analyzed.