Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors
Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors
复制标题
适用于纳米级器件和单电子晶体管的稳健电路和系统设计方法
DOI：
10.1109/tvlsi.2004.836292
复制
发表时间：
2004
影响因子：
2.8
通讯作者：
Y. Leblebici
中科院分区：
文献类型：
--
作者：
A. Schmid;Y. Leblebici
在本文中，各种电路和系统级的纳米级器件和单电子晶体管的设计挑战进行了讨论，重点是功能的鲁棒性和容错的观点。一套通用的准则是确定非常高密度的数字系统的设计使用固有的不可靠和容易出错的设备。提出了一种基于固定权重神经网络和多值逻辑的高度规则、冗余和可扩展的设计方法的基本原理。它表明，所提出的设计技术提供了显着提高免疫力的永久性和瞬态故障发生在晶体管级，它会导致在优雅的电路性能下降，响应于设备故障。
In this paper, various circuit and system level design challenges for nanometer-scale devices and single-electron transistors are discussed, with an emphasis to the functional robustness and fault tolerance point of view. A set of general guidelines is identified for the design of very high-density digital systems using inherently unreliable and error-prone devices. The fundamental principles of a highly regular, redundant, and scalable design approach based on fixed-weight neural networks and multiple-valued logic are presented. It is demonstrated that the proposed design technique offers significantly improved immunity to permanent and transient faults occurring at the transistor level, and that it results in graceful degradation of circuit performance in response to device failures.
使用相位量子逻辑电路的 SFQ 移位寄存器存储器的高密度集成
DOI：
--
发表时间：
2008
期刊：
影响因子：
--
作者：
Y. Natsume;M. Igarashi;K. Churei;N. Yoshikawa
通讯作者：
N. Yoshikawa