A reduced clock-swing flip-flop (RCSFF) for 63% power reduction
A reduced clock-swing flip-flop (RCSFF) for 63% power reduction
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DOI：
10.1109/4.668997
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发表时间：
1998-05
期刊：
影响因子：
--
通讯作者：
H. Kawaguchi;T. Sakurai
中科院分区：
文献类型：
--
作者：
H. Kawaguchi;T. Sakurai
提出了一种低摆幅时钟触发器（RCSFF），它由低摆幅时钟驱动器和一个包含漏电流截止机制的特殊触发器组成。与传统的触发器相比，RCSFF可以将VLSI的时钟系统功耗降低到三分之一。这种功率改进是通过将时钟摆幅降低到1 V来实现的。与传统触发器相比，RCSFF的面积和延迟也可以减少约20%。RCSFF还可以将长RC互连的RC延迟减少到一半。
A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leakage current cutoff mechanism. The RCSFF can reduce the clock system power of a VLSI down to one-third compared to the conventional flip-flop. This power improvement is achieved through the reduced clock swing down to 1 V. The area and the delay of the RCSFF can also be reduced by a factor of about 20% compared to the conventional flip-flop. The RCSFF can also reduce the RC delay of a long RC interconnect to one-half.