Small Footprint 6T-SRAM Design with MIV-Transistor Utilization in M3D-IC Technology
Small Footprint 6T-SRAM Design with MIV-Transistor Utilization in M3D-IC Technology
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DOI：
10.1109/iccd58817.2023.00027
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发表时间：
2023-11
期刊：
影响因子：
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通讯作者：
M. Vemuri;Umamaheswara Rao Tida
中科院分区：
文献类型：
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作者：
M. Vemuri;Umamaheswara Rao Tida
金属层间通孔（MIV）在单片三维集成电路（M3 D-IC）技术中提供顺序生长的衬底层之间的互连。MIV与周围的衬底形成一个金属-绝缘体-半导体（MIS）结构，从而潜在地干扰周围的设备。本文研究了MIV对附近的晶体管的特性，特别是漏电流的影响。仿真结果表明，由于内部放置的MIV，漏电流增加了高达528倍相比，没有内部MIV的晶体管，为假定的M3 D-IC工艺。然后，我们讨论了在M3 DIC技术中不使用内部MIV的6 T-SRAM实现，因为它们会显着增加泄漏。本文提出了一种利用MIS结构的小型SRAM单元。在2层晶体管级M3 D实现中，与传统SRAM设计相比，该方法的占用空间减少了19%。此外，SRAM单元的性能指标具体保持裕度、读取裕度、写入裕度、平均读取功率和平均写入功率与传统的两层晶体管级实现相比，对于所提出的两层晶体管级SRAM设计大大提高。
Metal inter-layer via (MIV) provides interconnects between sequentially grown substrate layers in monolithic three-dimensional integrated circuit (M3D-IC) technology. MIV with substrate around it forms a metal-insulator-semiconductor (MIS) structure, thus potentially interfering with devices around it. This paper studies the impact of the MIV on the characteristics of the nearby transistor, specifically the leakage current. Simulation results suggest that due to the internal placement of MIV, the leakage current increases by up to 528× compared with the transistor without internal MIV, for the assumed M3D-IC process. We then discuss the 6T-SRAM implementation in M3DIC technology without using internal MIVs as they significantly increase leakage. A compact SRAM cell by taking advantage of MIS structure is proposed in the paper. With this approach, the footprint is reduced by 19% compared with the conventional SRAM design in 2-layer transistor-level M3D implementation. In addition, the performance metrics of SRAM cell specifically hold margin, read margin, write margin, average read power, and average write power greatly improved for the proposed two-layer transistor-level SRAM design compared with the conventional two-layer transistor-level implementation.