A Reconfigurable Memory PUF Based on Tristate Inverter Arrays

A Reconfigurable Memory PUF Based on Tristate Inverter Arrays
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DOI:
10.1109/sips.2016.38
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发表时间:
2016-12
期刊:
2016 IEEE International Workshop on Signal Processing Systems (SiPS)
影响因子:
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通讯作者:
Yijun Cui;Chenghua Wang;Weiqiang Liu;Máire O’Neill
Yijun Cui;Chenghua Wang;Weiqiang Liu;Máire O’Neill
中科院分区:
其他
文献类型:
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作者:
Yijun Cui;Chenghua Wang;Weiqiang Liu;Máire O’Neill

文献摘要

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物理不可克隆函数(PUF)是一种很有前途的低成本安全解决方案的安全原语。它对于物联网(IoT)设备等资源受限的平台尤其有吸引力。提出了一种由两个交叉耦合的三态逆变器阵列组成的新型三态静态随机存取存储器(TSRAM)PUF设计。这种新的PUF结构能够重新配置交叉耦合的逆变器,以便它可以产生有效的挑战-响应对(CRP),而不使用任何额外的辅助处理,这在以前的基于存储器的PUF中是不可用的。通过UMC 65 nm工艺模拟和Xilinx Virtex-II现场可编程门阵列的实际实验,验证了所提出的TSRAM PUF的功能和性能。与以前的工作相比,提出的TSRAM PUF具有良好的唯一性和可靠性,并且使用最少的门来产生一个响应位。
A Physical Unclonable Function (PUF) is a promising security primitive for low cost security solutions. It is especially attractive for resource constrained platforms such as internet-of-things (IoT) devices. A novel Tristate Static Random Access Memory (TSRAM) PUF design consisting of two cross-coupled tristate inverter arrays is proposed in this paper. This new PUF structure is able to reconfigure the cross-coupled inverters so that it can produce effective challenge-response pairs (CRPs) without using any additional auxiliary processing, which is not available in previous memory based PUFs. The functionality and performance of the proposed TSRAM PUF is validated by both simulation with UMC 65nm technology and practical experimentation on a Xilinx Virtex-II FPGA. The proposed TSRAM PUF demonstrates good uniqueness and reliability and it uses the smallest number of gates to produce one response bit compared with previous works.