NBTI Monitoring and Design for Reliability in Nanoscale Circuits
NBTI Monitoring and Design for Reliability in Nanoscale Circuits
复制标题
纳米级电路可靠性的 NBTI 监测和设计
DOI：
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
F. Catthoor
中科院分区：
文献类型：
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作者：
Seyab Khan;N. Haron;S. Hamdioui;F. Catthoor
负偏压温度不稳定性(NBTI)已成为纳米时代电路可靠性的主要威胁之一。本文提出了一种监测和容忍纳米级电路中NBTI的新技术。首先，模拟了NBTI对门输出转换时间的影响，仿真结果表明，NBTI可以使门输出转换时间增加8.56%。其次，提出了一种基于门输出跃迁时间的NBTI影响监测方案。该方案将过渡时间增量转换为灵敏度为0.50 mV=ps的电压，仿真结果表明，过渡时间增量可使监控电路输出电压增加高达80 mV。第三，提出了一种通过对PMOS晶体管施加正体偏置来减小NBTI影响的可靠性设计，在33级环形振荡器上进行的模拟表明，该技术在10年的工作寿命内将NBTI影响降低了34%。为了说明该方法的有效性，还分析了该方法的泄漏开销。
Negative Bias Temperature Instability (NBTI) has become one of the major threats to circuit reliability in nanoscale-era. This paper presents a novel technique to monitor and tolerate NBTI in nanoscale circuits. First, it models NBTI impact on the gate output transition time, the simulation results show that NBTI can cause up to 8.56% increment to the transition time. Second, it presents a scheme to monitor the NBTI impact, the scheme is based on measuring transition time of the gate output. The proposed scheme converts the transition time increment into a voltage with a sensitivity of 0.50mV = ps, the simulation results show that the transition time increment can cause up to 80mV increment in the monitoring circuit output voltage. Third, it proposes a design for reliability technique to mitigate NBTI impact by applying a positive body bias to the PMOS transistors, simulations carried out on a 33-stage ring oscillator reveal that the technique reduces NBTI impact by 34% in 10 years operational life. To show its effectiveness, leakage overhead of the proposed technique is also analyzed.