Single event effects on CVSL and CMOS exclusive-OR (EX-OR) circuits
Single event effects on CVSL and CMOS exclusive-OR (EX-OR) circuits
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DOI：
10.1109/radecs.2009.5994567
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发表时间：
2009-09
期刊：
影响因子：
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通讯作者：
H. Hatano
中科院分区：
文献类型：
--
作者：
H. Hatano
用SPICE研究了单粒子瞬态效应对级联电压开关逻辑异或电路的影响。采用双多晶硅双金属N阱CMOS工艺成功地制作了CVSL和CMOS链式电路。这两个电路已被证实，以正确的功能，由制造的芯片测量。SET仿真结果证实了CVSL电路对SET的容忍度有所提高。将CVSL EX-OR的SET容限与常规CMOS EX-OR的SET容限进行了比较，表明CVSL是SET容限星载逻辑电路的候选电路。
Single event transient (SET) effects on cascade voltage switch logic (CVSL) exclusive-OR (EX-OR) circuits have been investigated using SPICE. CVSL and CMOS chain circuits have been successfully fabricated utilizing a double polysilicon double metal N-well CMOS process. Both circuits have been confirmed to function correctly by the fabricated chip measurements. SET simulation results have confirmed that the CVSL circuits have increased tolerance to SET. SET tolerance for the CVSL EX-OR is compared to that for the conventional CMOS EX-OR, showing that the CVSL is a candidate for a SET tolerant spaceborne logic circuit.