An Interactive Design Space Exploration Tool for Dependable Integrated Circuits
An Interactive Design Space Exploration Tool for Dependable Integrated Circuits
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DOI：
10.1109/dsd.2016.83
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发表时间：
2016-08
期刊：
影响因子：
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通讯作者：
Stefan Scharoba;H. Vierhaus
中科院分区：
文献类型：
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作者：
Stefan Scharoba;H. Vierhaus
晶体管特征尺寸的缩小导致集成电路更容易受到各种故障的影响。为了满足可靠性需求，必须应用适当的容错技术。这给集成电路的设计过程增加了另一项具有挑战性的任务，其中必须包括对不同容错实现的成本和收益的仔细评估。本文提出了一种工具，该工具通过自动评估结构化VHDL中指定的电路中基于硬件冗余的容错的使用来支持这种设计空间探索。描述了该工具的主要特性及其在已建立的EDA流中的集成。
The downscaling of transistor feature sizes has led to integrated circuits that are more susceptible to various fault effects. In order to meet dependability requirements, appropriate fault tolerance techniques have to be applied. This adds another challenging task to the design process of integrated circuits, which has to include a careful evaluation of costs and benefits of different fault-tolerant implementations. This paper presents a tool that supports this design space exploration by automatically evaluating the use of hardware redundancy-based fault tolerance for circuits specified in structural VHDL. The tool's main features as well as its integration in established EDA flows are described.