Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity
Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity
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DOI：
10.1038/s41534-023-00679-8
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发表时间：
2023-02-22
影响因子：
7.6
通讯作者：
Gonzalez-Zalba，M. F.
中科院分区：
文献类型：
--
作者：
Crawford，O.;Cruise，J. R.;Gonzalez-Zalba，M. F.
受现有硅量子硬件规模扩大的挑战的启发，我们提出了一种具有低编译开销的2d自旋量子位架构。该架构基于硅纳米线分裂栅极晶体管，形成自旋量子位的一维链，并允许在邻居之间执行两个量子位操作。我们引入了一个硅结，它可以通过自旋穿梭和交换操作将四根纳米线耦合成二维排列。然后，我们提出了一个模块化的稀疏二维自旋量子位结构与单位细胞的对角线方向的正方形与纳米线沿着的边缘和角落上的结。针对嘈杂的中间尺度量子（NISQ）的示威者，我们表明，建议的架构允许编译策略，优于方法的一维链，并表现出良好的缩放性能，使权衡编译开销和托管控制电子在每个广场内通过调整纳米线长度。所提出的架构的一个吸引人的特点是它的可制造性使用互补金属氧化物半导体（CMOS）制造工艺。
Inspired by the challenge of scaling-up existing silicon quantum hardware, we propose a 2d spin-qubit architecture with low compilation overhead. The architecture is based on silicon nanowire split-gate transistors which form 1d chains of spin-qubits and allow the execution of two-qubit operations among neighbors. We introduce a silicon junction which can couple four nanowires into 2d arrangements via spin shuttling andSwapoperations. We then propose a modular sparse 2d spin-qubit architecture with unit cells of diagonally-oriented squares with nanowires along the edges and junctions on the corners. Targeting noisy intermediate-scale quantum (NISQ) demonstrators, we show that the proposed architecture allows for compilation strategies which outperform methods for 1d chains, and exhibits favorable scaling properties which enable trading-off compilation overhead and colocation of control electronics within each square by adjusting the nanowire length. An appealing feature of the proposed architecture is its manufacturability using complementary-metal-oxide-semiconductor (CMOS) fabrication processes.