Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array
Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array
复制标题
开发低复杂度全数字锁频环作为现场可编程门阵列的 500 MHz 参考时钟发生器
DOI：
10.1049/iet-cds.2013.0175
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发表时间：
2014
期刊：
影响因子：
--
通讯作者：
Sang
中科院分区：
文献类型：
--
作者：
S. Yuwono;Seok;Gi;Han;Sang
作者报告了一种片上500 MHz参考时钟发生器的开发，作为现场可编程门阵列时钟管理器的一部分。该发生器采用全数字锁频环（ADFLL）的形式实现，具有低复杂度和高模块化的结构。对于ADFLL的开发，他们提出了一种新电路，该电路采用两个欠采样1位ΔΣ频率-数字转换器将频率差转换为比例分布脉宽。通过将所提出的电路与传统的相频检测器相结合，实现了频率比较器，并可以指示其两个输入频率条件，即(i)等于，（ii）低于或（iii）高于。采用该频率比较器的ADFLL采用90 nm CMOS技术实现。ADFLL在1.2 V电源下消耗2.64 mW，工作频率为500 MHz，由10 MHz参考时钟驱动时，锁定时间约为50µs，频率精度为99.2%。
The authors report the development of an on-chip 500 MHz reference clock generator as a part of a clock manager for a field-programmable gate array. The generator is implemented in the form of an all-digital frequency locked loop (ADFLL) in architecture of low complexity and high modularity. For the development of the ADFLL, they propose a new circuit that employs two under-sampled 1-bit ΔΣ frequency-to-digital converters to convert a frequency difference into a proportional distributed pulsewidth. By the combination of the proposed circuit with a conventional phase-and-frequency detector, a frequency comparator is implemented and can indicate its two input frequency conditions, that is, (i) equal to, (ii) lower than or (iii) higher than. The ADFLL which adopts the proposed frequency comparator is implemented in a 90 nm CMOS technology. Consuming 2.64 mW from a 1.2 V supply, the ADFLL shows about 50 µs of locking time at the frequency accuracy of 99.2% while operating at 500 MHz and being driven by a 10 MHz reference clock.