Memristor Bridge Synapse-Based Neural Network and Its Learning
Memristor Bridge Synapse-Based Neural Network and Its Learning
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DOI：
10.1109/tnnls.2012.2204770
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发表时间：
2012-09-01
影响因子：
10.4
通讯作者：
Chua, Leon O.
中科院分区：
文献类型：
--
作者：
Adhikari, Shyam Prasad;Yang, Changju;Chua, Leon O.
提出了一种基于忆阻器桥突触的多层神经网络的模拟硬件结构及其学习方案。在所提出的架构中使用忆阻器桥突触解决了模拟神经网络实现中关于非易失性权重存储的主要问题之一。为了补偿忆阻器桥突触的空间非均匀性和非理想响应，还提出了一种适用于所提出的神经网络架构的改进的芯片在环学习方案。在所提出的方法中，初始学习在软件中进行，并且通过独立地学习网络的每个单层神经元，由硬件网络学习软件训练的网络的行为。单层神经元学习的前向计算在电路硬件上实现，然后是由主机辅助的权重更新阶段。与传统的芯片在环学习不同，由于忆阻器桥突触和所提出的学习方案，消除了在每个时期中用于计算权重更新的突触权重的读出的需要。硬件架构沿着的成功实施提出的学习上的三位奇偶校验网络，并在汽车检测网络。
Analog hardware architecture of a memristor bridge synapse-based multilayer neural network and its learning scheme is proposed. The use of memristor bridge synapse in the proposed architecture solves one of the major problems, regarding nonvolatile weight storage in analog neural network implementations. To compensate for the spatial nonuniformity and nonideal response of the memristor bridge synapse, a modified chip-in-the-loop learning scheme suitable for the proposed neural network architecture is also proposed. In the proposed method, the initial learning is conducted in software, and the behavior of the software-trained network is learned by the hardware network by learning each of the single-layered neurons of the network independently. The forward calculation of the single-layered neuron learning is implemented on circuit hardware, and followed by a weight updating phase assisted by a host computer. Unlike conventional chip-in-the-loop learning, the need for the readout of synaptic weights for calculating weight updates in each epoch is eliminated by virtue of the memristor bridge synapse and the proposed learning scheme. The hardware architecture along with the successful implementation of proposed learning on a three-bit parity network, and on a car detection network is also presented.