A case for routing cache on HPC switches
A case for routing cache on HPC switches
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DOI：
10.1587/comex.1.49
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发表时间：
2012-06
期刊：
影响因子：
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通讯作者：
S. Ishida;M. Koibuchi;H. Nishi
中科院分区：
文献类型：
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作者：
S. Ishida;M. Koibuchi;H. Nishi
大型众核并行应用程序对通信延迟变得敏感，这表明在高性能计算系统中需要低延迟网络。交换机时延是网络时延的主要因素。为了减少网络延迟，我们在交换机上利用路由缓存。基于片上CAM（内容可寻址存储器）的表查找的路由决策会产生显著的延迟，但是，使用片上小型路由缓存可以在命中时绕过它。我们的模拟结果表明，只有256个条目的路由缓存命中98%以上的4k主机系统与矩阵转置传输，和1024个条目的路由缓存不仅提高了高达16%的数据包延迟，但也高达18%的网络吞吐量。
: Large many-core parallel applications become sensitive to communication latencies, suggesting the need for low-latency networks in high-performance computing systems. Switch delay dominates network latencies. To reduce the network latencies, we exploit routing cache on a switch. Routing decision based on off-chip CAM (Content Addressable Memory)-based table lookup imposes a significant delay, however, using on-chip small routing cache can bypass it when it hits. Our simulation results show that the only 256-entry routing cache hits 98% on over 4k-host systems with the matrix-transpose traffic, and the 1024-entry routing cache improves not only up to 16% of packet latency but also up to 18% of network throughput.