A novel CMOS logic style with data independent power consumption
A novel CMOS logic style with data independent power consumption
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一种新颖的 CMOS 逻辑风格，具有与数据无关的功耗
DOI：
10.1109/iscas.2005.1464776
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
A. Trifiletti
中科院分区：
文献类型：
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作者：
M. Aigner;S. Mangard;R. Menicocci;M. Olivieri;G. Scotti;A. Trifiletti
我们提出了一种新颖的动态CMOS逻辑样式，以保护安全设备免受电力攻击。该逻辑基于具有3个可能状态的信号，并具有功耗的运行，理想地独立于逻辑值和数据序列。我们已经设计了一组逻辑门和一个flip-flop，并将这些逻辑门与静态互补的CMOS实现进行了比较，以数据与功耗，速度，区域和总功率耗散之间的相关性。
We propose a novel dynamic CMOS logic style to protect security devices against power attacks. The logic is based on signals with 3 possible states and operates with a power consumption ideally independent of both the logic values and the sequence of data. We have designed a set of logic gates and a flip-flop and compared those to static complementary CMOS implementations in terms of correlation between data and power consumption, speed, area, and total power dissipation.