Transport properties of sub-10-nm planar-bulk-CMOS devices
Transport properties of sub-10-nm planar-bulk-CMOS devices
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亚 10 纳米平面体 CMOS 器件的传输特性
DOI：
10.1109/iedm.2004.1419178
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发表时间：
2004
期刊：
影响因子：
--
通讯作者：
H. Kawaura
中科院分区：
文献类型：
--
作者：
H. Wakabayashi;T. Ezaki;M. Hane;S. Yamagami;N. Ikarashi;K. Takeuchi;T. Yamamoto;T. Mogami;T. Ikezawa;T. Sakamoto;H. Kawaura
亚 10 纳米平面体 MOSFET 的传输特性已得到评估。对于低温下的亚 10 nm CMOS 器件，可以清楚地观察到源极和漏极 (S/D) 区域之间的直接隧道电流，不仅具有栅极长度效应，而且还具有“漏极诱导隧道调制 (DITM)”效应。此外，量子力学（QM）模拟表明，隧道电流随着温度和栅极电压的增加而增加，即使在300 K下，对亚阈值电流的贡献也很大。因此，强烈要求降低电源电压，以抑制亚10纳米CMOS器件即使在室温操作下的DITM效应。
Transport properties of sub-10-nm planar bulk MOSFETs have been evaluated. Direct-tunneling currents between source and drain (S/D) regions with not only the gate-length effects but also "drain-induced tunneling modulation (DITM)" effects are clearly observed for sub-10-nm CMOS devices at low temperature. Moreover, a quantum mechanical (QM) simulation reveals that the tunneling currents increase with the increase in the temperatures and gate voltages, resulting in the significant contribution to the subthreshold current even at 300 K. Therefore, it is strongly required that the supply-voltage should be reduced, to suppress the DITM effects for the sub-10-nm CMOS devices even under the room-temperature operations.