Experimental studies on SAT-based test pattern generation for industrial circuits
Experimental studies on SAT-based test pattern generation for industrial circuits
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基于SAT的工业电路测试模式生成实验研究
DOI：
10.1109/icasic.2005.1611489
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
F. Hapke
中科院分区：
文献类型：
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作者：
Junhao Shi Gorschwin;Fey Rolf Drechsler;Andreas Glowatz;Juirgen Schloffel;F. Hapke
随着集成电路规模的不断增大，传统的自动测试生成方法已经达到了极限。另一方面，最近的进展，解决布尔可满足性（SAT）问题的算法允许应用到大型实例。这表明，利用现代SAT技术的ATPG。在这里，我们提出了一个基于SAT的ATPG工具，适用于大型工业电路。不同的SAT-求解器的性能进行了实验评估，并显示出潜在的问题特定的problem。进一步的实验表明，大多数故障可以非常有效地分类独立的电路大小
Due to the ever increasing size of integrated circuits classical methods for automatic test pattern generation (ATPG) reach their limits. On the other hand recent advances in algorithms to solve the Boolean satisfiability (SAT) problem allow the application to large instances. This suggests to exploit modern SAT techniques for ATPG. Here, we present a SAT-based ATPG tool that is applicable to large industrial circuits. The performances of different SAT-solvers are experimentally evaluated and the potential for problem specific heuristics is shown. Further experiments show that most of the faults can be classified very efficiently independently of the circuit size