An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at VDD=0 V Achieving Zero Leakage With <400-ns Wakeup Time for ULP Applications
An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at VDD=0 V Achieving Zero Leakage With <400-ns Wakeup Time for ULP Applications
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DOI：
10.1109/jssc.2013.2284367
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发表时间：
2014-01-01
影响因子：
5.4
通讯作者：
McAdams, Hugh P.
中科院分区：
文献类型：
--
作者：
Khanna, Sudhanshu;Bartling, Steven C.;McAdams, Hugh P.
本文提出了一种基于非易失性逻辑（NVL）的32b微控制器片上系统（SoC），它在接收电源中断时备份其工作状态（所有触发器），在睡眠模式下具有零泄漏，并且在上电时需要不到400 ns的时间恢复系统状态。基于fe - cap的非易失性微型阵列备份机器状态，并允许芯片在电源循环后立即唤醒。如果没有NVL，芯片要么必须保持所有触发器通电，导致待机功率过高，要么在通电后重新启动时浪费能量和时间。NVL允许系统使用更少泄漏的进程来实现更高的性能/更低的动态功率，同时在休眠模式下仍然没有泄漏。提出了优化的系统、架构和电路技术，使NVL在SoC面积仅增加3.6%的情况下变得实用。由于SoC中添加了非易失性元件，因此可靠性和可测试性必须成为设计的关键特征。这是第一个具有可测量的NVL位单元读取信号裕度数据和广泛的测试和调试功能的NVL SoC。该芯片采用商用130纳米低漏工艺制造，并使用单个1.5 v电源。
This paper presents a nonvolatile logic (NVL)-based 32-b microcontroller system-on-chip (SoC) that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400 ns to restore the system state upon power-up. Nonvolatile Fe-Cap-based mini-arrays backup the machine state and allow the chip to wake up instantly after a power cycle. Without NVL, a chip would either have to keep all flip-flops powered, resulting in high standby power, or waste energy and time rebooting after power-up. NVL allows systems to use leakier processes to achieve higher performance/lower dynamic power while still having zero leakage in the sleep mode. Optimized system, architecture, and circuit techniques are presented that make NVL practical by adding only 3.6% to the SoC area. Since nonvolatile elements are added to the SoC, reliability and testability have to be key features of the design. This is the first NVL SoC with measured NVL bitcell read signal margin data and extensive test and debug capabilities. The chip is fabricated in a commercial 130-nm low-leakage process and uses a single 1.5-V power supply.