Energy Efficient Digital Data Link
Energy Efficient Digital Data Link
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节能数字数据链
DOI：
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发表时间：
2017
影响因子：
1.8
通讯作者：
J. Bardin
中科院分区：
文献类型：
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作者：
Prasana Ravindran;Su;Wei;S. Sarwana;V. Dotsenko;J. Tang;S. Ruotolo;D. Gupta;J. Bardin
将单通量量子（SFQ）逻辑的高速和低压摆幅输出有效地放大到适合与室温电子器件连接的水平一直是超导电子器件领域长期存在的挑战。在这项工作中，我们研究了在 4 K 下使用有损无源匹配网络的可行性，其中一对差分 100 低噪声放大器分别散热至 18 K 和 50 K 级。这些放大器采用 120 nm SiGe BiCMOS 技术实现。放大链是直流耦合的，小信号链路增益经测量约为 48 dB。两个放大级的功耗均为 6.3 mW。使用高速差分不归零信号在 21 K 下测量该链，该信号的幅度与超导电路的预期相当，并且在高达 30 Gb/s 的数据速率下观察到清晰的眼图。当从 SFQ/dc 接口驱动时，也对链条进行了测量，第一增益级散热至 9 K。在此配置中，观察到干净的眼图至 5 Gb/s，速度限制与封装寄生效应有关。
Efficiently amplifying the high-speed and low-voltage swing outputs of single flux quantum (SFQ) logic to levels that are suitable for interfacing with room temperature electronics has been a long-standing challenge in the field of superconducting electronics. In this work, we investigate the feasibility of using a lossy passive matching network at 4 K, with a pair of differential 100 low-noise amplifiers heatsunk to 18 K and 50 K stages, respectively. The amplifiers were implemented in a 120 nm SiGe BiCMOS technology. The amplification chain is dc coupled and the small-signal link gain was measured to be approximately 48 dB. The power consumption of each of the two amplification stages was 6.3 mW. The chain was measured at 21 K using a high-speed differential nonreturn-to-zero signal having amplitude commensurate with what one would expect from a superconducting circuit, and clean eye diagrams were observed for data rates as high as 30 Gb/s. The chain was also measured when driven from an SFQ/dc interface, with the first gain stage heatsunk to 9 K. In this configuration, clean eye diagrams were observed to 5 Gb/s, with the speed limitation being related to packaging parasitics.