Reducing Power and Cycle Requirement for FFT of ECG Signals through Low Level Arithmetic Optimizations for Cardiac Implantable Devices.
Reducing Power and Cycle Requirement for FFT of ECG Signals through Low Level Arithmetic Optimizations for Cardiac Implantable Devices.
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通过心脏植入设备的低级算术优化来降低 ECG 信号 FFT 的功率和周期要求。
DOI：
10.1166/jolpe.2016.1423
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发表时间：
2016
影响因子：
--
通讯作者：
John,Eugene
中科院分区：
文献类型：
--
作者：
Mostafa,Safwat;John,Eugene
在几乎所有学科中，快速傅里叶变换或FFT仍然是计算离散傅立叶变换的事实上的标准。在嵌入式生物医学应用中，高效的信号处理算法如FFT用于频谱分析是不可或缺的。FFT是一种O(Nlog2N)算法，需要使用浮点数进行复杂的乘法和加法。在功率极其有限的嵌入式系统上，例如心脏起搏器，浮点运算的周期非常密集，并且在功耗方面非常昂贵。这项工作旨在利用心电图的重复性质来减少执行128点FFT例程所需的总算术运算的数量。利用简单的查找表概念，该算法能够提高计算心电信号FFT的性能和能量占用。在32位嵌入式平台上实现了标准分裂基2 FFT程序的计算速度提高了9.22%，电池寿命提高了10.1%。这一概念使用从PhysioNet收集的实际心电数据进行了测试。
The Fast Fourier Transform or FFT remains to be the de facto standard in almost all disciplines for computing discrete Fourier transform. In embedded biomedical applications, efficient signal processing algorithms such as FFT for spectrum analysis are indispensable. The FFT is an O(Nlog2 N) algorithm which requires complex multiplication and addition using floating point numbers. On extremely power constrained embedded systems such as cardiac pacemakers, floating point operations are very cycle intensive and costly in terms of power. This work aims to exploit the repetitive nature of the Electrocardiogram (ECG) to reduce the number of total arithmetic operations required to execute a 128 point FFT routine. Using the simple concept of lookup tables, the proposed algorithm is able to improve both the performance and energy footprint for computing the FFT of the ECG data. An increase of 9.22% in computational speed and an improvement of 10.1% in battery life on a 32 bit embedded platform for a standard split-radix-2 FFT routine is achieved. The concept is tested using actual ECG data collected from PhysioNet.