Route packets, not wires: on-chip interconnection networks
Route packets, not wires: on-chip interconnection networks
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DOI：
10.1109/dac.2001.156225
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发表时间：
2001-06
期刊：
影响因子：
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通讯作者：
W. Dally;Brian Towles
中科院分区：
文献类型：
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作者：
W. Dally;Brian Towles
使用片上互连网络代替ad-hoc全局布线结构，在芯片上进行顶层布线，并促进模块化设计。通过这种方法，系统模块（处理器、存储器、外围设备等）通过在网络上互相发送数据包进行通信。结构化的网络布线提供了良好控制的电气参数，消除了定时迭代，并使高性能电路的使用，以减少延迟和增加带宽。实现片上网络所需的面积开销不大，我们估计为6.6%。本文介绍了片上网络的概念，勾勒了一个简单的网络，并讨论了这些网络的结构和设计中的一些挑战。
Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules (processors, memories, peripherals, etc...) communicate by sending packets to one another over the network. The structured network wiring gives well-controlled electrical parameters that eliminate timing iterations and enable the use of high-performance circuits to reduce latency and increase bandwidth. The area overhead required to implement an on-chip network is modest, we estimate 6.6%. This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.