Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device
Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device
复制标题
利用单元内误码特性改进移动设备中基于 MLC NAND 闪存的存储的最小和 LDPC 解码
DOI：
10.1109/tvlsi.2016.2535224
复制
发表时间：
2016-08-01
影响因子：
2.8
通讯作者：
Zhang, Tong
中科院分区：
文献类型：
--
作者：
Sun, Hongbin;Zhao, Wenzhe;Zhang, Tong
每单元多电平(MLC)技术显著提高了存储密度，但也对NAND闪存的数据完整性提出了严峻的挑战。这使得低密度奇偶校验(LDPC)码和软判决存储检测成为下一代基于闪存的固态存储设备中不可或缺的部分。然而，LDPC码的使用不可避免地增加了存储器读取延迟，从而降低了速度性能。针对移动设备中MLC NAND闪存中存在的小区内误码率和数据相关性不均衡的现象，提出了两种基于小区内数据放置交织和小区内数据相关性感知的LDPC译码技术，有效地提高了移动设备中基于MLC NAND闪存的LDPC译码吞吐量和能量效率。实验结果表明，利用小区内的误码特性，在不超过0.2%的面积开销的情况下，所提出的方法可以使LDPC译码吞吐量提高84.6%，能耗降低33.2%。
A multilevel per cell (MLC) technique significantly improves the storage density, but also poses serious data integrity challenge for NAND flash memory. This consequently makes the low-density parity-check (LDPC) code and the soft-decision memory sensing become indispensable in the next-generation flash-based solid-state storage devices. However, the use of LDPC codes inevitably increases memory read latency and, hence, degrades speed performance. Motivated by the observation of intracell unbalanced bit error probability and data dependence in the MLC NAND flash memory, this paper proposes two techniques, i.e., intracell data placement interleaving and intracell data dependence aware LDPC decoding, to efficiently improve the LDPC decoding throughput and energy efficiency for the MLC NAND flash-based storage in a mobile device. Experimental results show that, by exploiting the intracell bit-error characteristics, the proposed techniques together can improve the LDPC decoding throughput by up to 84.6% and reduce the energy consumption by up to 33.2% while only incurring less than 0.2% silicon area overhead.