Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs
Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs
复制标题
Compact-2D：构建商业品质面对面键合 3D IC 的物理设计方法
DOI：
10.1145/3177540.3178244
复制
发表时间：
2018
期刊：
影响因子：
--
通讯作者：
S. Lim
中科院分区：
文献类型：
--
作者：
B. W. Ku;Kyungwook Chang;S. Lim
晶圆粘合技术的最新进步提供了面对面（F2F）键合3D IC的细粒度和硅空间3D互连。在本文中，我们提出了一种全芯片RTL到GDSII物理设计解决方案，以构建高密度和商业质量的两层F2F键入3D IC。名为Shrunk-2D（S2D）的最先进的流量要求将标准单元和互连缩小50％，以适合两层设计的目标3D足迹。不幸的是，这需要商业场所/路线引擎处理一个节点较小的几何形状，这可能是具有挑战性且昂贵的。我们名为Compact-2D（C2D）的流动不需要任何几何形状收缩。取而代之的是，C2D使用缩放的互连RC寄生虫实现2D IC，并将布局与F2F设计足迹合并。此外，C2D还提供后分区优化，该优化可有效固定由Inter-tier 3D路由引起的定时违规行为，这在S2D中完全缺少。最后，我们提出了一种回收最终GDSII生成后分区优化的路由结果的方法。我们的实验结果表明，在ISO绩效时，C2D可提供高达26.8％的功率，而在商业2D IC上节省了15.6％的硅面积，而没有任何路由资源开销。
The recent advancement of wafer bonding technology offers fine-grained and silicon-space overhead-free 3D interconnections in face-to-face (F2F) bonded 3D ICs. In this paper, we propose a full-chip RTL-to-GDSII physical design solution to build high-density and commercial-quality two-tier F2F-bonded 3D ICs. The state-of-the-art flow named Shrunk-2D (S2D) requires shrinking of standard cells and interconnects by a factor of 50% to fit into the target 3D footprint of a two-tier design. This, unfortunately, necessitates commercial place/route engines that handle one node smaller geometries, which can be challenging and costly. Our flow named Compact-2D (C2D) does not require any geometry shrinking. Instead, C2D implements a 2D IC with scaled interconnect RC parasitics, and contracts the layout to the F2F design footprint. In addition, C2D offers post-tier-partitioning optimization that is shown to be effective in fixing timing violations caused by inter-tier 3D routing, which is completely missing in S2D. Lastly, we present a methodology to recycle the routing result of post-tier-partitioning optimization for final GDSII generation. Our experimental results show that at iso-performance, C2D offers up to 26.8% power reduction and 15.6% silicon area savings over commercial 2D ICs without any routing resource overhead.