A motion planning processor on reconfigurable hardware
A motion planning processor on reconfigurable hardware
复制标题
可重构硬件上的运动规划处理器
DOI：
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
Burchan Bayazit
中科院分区：
文献类型：
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作者：
N. Atay;Burchan Bayazit
运动规划算法使我们能够为运动物体找到可行的路径。这些算法利用可行性检查来区分有效路径和无效路径。不幸的是，这种检查的计算代价很高，降低了运动规划算法的有效性。然而，通过使用硬件加速来加快可行性检查，我们可以大大提高运动规划算法的性能。当然，这种加速并不局限于可行性检查；运动规划算法的其他组件也可以使用专门设计的硬件来加速。现场可编程门阵列（FPGA）是支持这种加速的一个很好的平台。FPGA是可以在运行时重新编程的数字门的集合，也就是说，它可以用作为给定任务重新配置自身的CPU。本文研究了基于FPGA的运动规划处理器的可行性，并对其性能进行了评价。为了充分利用其高度并行性和模块化结构，我们的处理器在其核心采用了概率路线图方法。模块化使我们能够将可行性标准替换为其他标准。可重构性使我们能够以不同的角色运行处理器，例如运动规划协处理器、自主运动规划处理器或专用碰撞检测芯片。实验表明，这种处理器不仅可行，而且可以大大提高现有算法的性能
Motion planning algorithms enable us to find feasible paths for moving objects. These algorithms utilize feasibility checks to differentiate valid paths from invalid ones. Unfortunately, the computationally expensive nature of such checks reduces the effectiveness of motion planning algorithms. However, by using hardware acceleration to speed up the feasibility checks, we can greatly enhance the performance of the motion planning algorithms. Of course, such acceleration is not limited to feasibility checks; other components of motion planning algorithms can also be accelerated using specially designed hardware. A field programmable gate array (FPGA) is a great platform to support such an acceleration. An FPGA is a collection of digital gates which can be reprogrammed at run time, i.e., it can be used as a CPU that reconfigures itself for a given task. In this paper, we study the feasibility of an FPGA based motion planning processor and evaluate its performance. In order to leverage its highly parallel nature and its modular structure, our processor utilizes the probabilistic roadmap method at its core. The modularity enables us to replace the feasibility criteria with other ones. The reconfigurability lets us run our processor in different roles, such as a motion planning co-processor, an autonomous motion planning processor or dedicated collision detection chip. Our experiments show that such a processor is not only feasible but also can greatly increase the performance of current algorithms