Energy Efficient Low Area Error Tolerant Adder with Higher Accuracy
Energy Efficient Low Area Error Tolerant Adder with Higher Accuracy
复制标题
具有更高准确度的节能低面积容错加法器
DOI：
10.1007/s00034-014-9749-x
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发表时间：
2014
期刊：
影响因子：
--
通讯作者：
H. Kittur
中科院分区：
文献类型：
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作者：
R. Sakthivel;H. Kittur
对真实的时间高端数字信号/图像处理的需要需要具有合理精度的非常巨大的计算。本文提出了两种低面积容错加法器（ELAETA-I和ELAETA-II），它们可以满足大多数信号处理应用的需要。这项工作减少了计算量和精度之间的权衡。ELAETA电路的不准确部分中的误差敏感块预先确定进位，并允许同时计算不准确的部分和值，从而与容错加法器（ETA-I）相比将最大延迟减少55%，并且将进位适当地添加到准确部分，使精度比现有ETA-I和ETA-II提高20%。加法器的不精确部分是用所提出的新的或门单元和传输晶体管单元来构造的，与现有的ETA-I相比，它分别减少了10个和12个晶体管。此外，还包括一个新的数据感知块，它将评估输入序列并适当地激活/停用某些计算模块，从而减少切换活动。仿真结果表明，所提出的ELAETA电路的功率延迟积减少了59%，面积减少了20%左右。整个电路使用Cadence Virtuoso构建，并使用TSMC的180和45 nm工艺节点的Spectre进行仿真。
The need for real time high end digital signal/image processing demands a very huge computation with a reasonable accuracy. This paper presents two energy efficient low area error tolerant adders (ELAETA-I and ELAETA-II) which could cater the needs of most signal processing application. This work has reduced the tradeoff that exists between the amount of computation and the accuracy. The error sensitive block in the inaccurate part of the ELAETA circuit, predetermines the carry and allows the simultaneous calculation of inaccurate part sum value, thereby reducing the maximum delay by 55 % compared to error-tolerant adder (ETA-I) and its appropriate addition of carry to the accurate part increases the accuracy by 20 % over the existing ETA-I and ETA-II. The inaccurate part of the adder is being constructed with the proposed new OR gate cell and the pass transistor cell, which has reduced the number of transistor by 10 and 12, respectively, compared with the existing ETA-I. In addition a new data aware block has been included which will evaluate the input sequence and appropriately activate/de-activate certain computation modules and there by reduce the switching activity. The simulation result of the proposed ELAETA circuits shows that the power delay product has reduced by 59 % and area around 20 %. The whole circuit has been constructed using Cadence Virtuoso and the simulation done using Spectre with 180 and 45 nm technology node from TSMC.