An accurate analysis of the effects of soft errors in the instruction and data caches of a pipelined microprocessor
An accurate analysis of the effects of soft errors in the instruction and data caches of a pipelined microprocessor
复制标题
准确分析流水线微处理器指令和数据缓存中软错误的影响
DOI：
10.1109/date.2003.1253674
复制
发表时间：
2003
期刊：
影响因子：
--
通讯作者：
M. Violante
中科院分区：
文献类型：
--
作者：
M. Rebaudengo;M. Reorda;M. Violante
指令和数据高速缓存是众所周知的架构解决方案，其允许显著提高高端处理器的性能。由于它们对软错误的敏感性，它们通常在安全关键应用中被禁用，从而牺牲性能以提高可靠性。在本文中，我们报告了一个准确的分析软错误的指令和数据高速缓存的软核实现的可重构体系结构的影响。由于我们开发了一个有效的基于模拟的故障注入环境，我们能够在本文中提出了一个广泛的分析软错误的影响，在不同的内存配置下运行几个应用程序的处理器。我们遵循的程序允许精确计算处理器故障率时，该高速缓存启用，即使不诉诸昂贵的辐射实验。
Instruction and data caches are well known architectural solutions that allow significant improvement in the performance of high-end processors. Due to their sensitivity to soft errors, they are often disabled in safety critical applications, thus sacrificing performance for improved dependability. In this paper, we report an accurate analysis of the effects of soft errors in the instruction and data caches of a soft core implementing the SPARC architecture. Thanks to an efficient simulation-based fault injection environment we developed, we are able to present in this paper an extensive analysis of the effects of soft errors on a processor running several applications under different memory configurations. The procedure we followed allows the precise computation of the processor failure rate when the cache is enabled even without resorting to expensive radiation experiments.