Deep level transient spectroscopy and capacitance-voltage study of dislocations and associated defects in SiGe∕Si heterostructures
Deep level transient spectroscopy and capacitance-voltage study of dislocations and associated defects in SiGe∕Si heterostructures
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SiGe/Si 异质结构中位错和相关缺陷的深能级瞬态光谱和电容电压研究
DOI：
10.1063/1.2903154
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发表时间：
2008
影响因子：
3.2
通讯作者：
G. Rozgonyi
中科院分区：
文献类型：
--
作者：
Jinggang Lu;Yongkook Park;G. Rozgonyi
用深能级瞬态谱和电容-电压技术研究了三种不同Ge含量的SiGe scinSi异质结构。DLTS结果显示，在80 ~ 250 K温度范围内，样品中存在一个宽的陷阱带。25%SiGe样品的Arrhenius图显示三个陷阱能级分别在价带以上0.28、0.31和0.43eV。通过改变反向偏压和比较不同Ge含量的样品，发现陷阱能级随着Ge含量的增加而向价带移动。电容-电压数据表明，SiGe渐变层中的受主陷阱能级从生长态样品中的40× 1013 cm −3急剧下降到800°C以上退火后的4× 1013 cm −3。基于它们的电荷状态和热退火行为，我们认为大部分的生长在受主能级可能是由于位错慢跑拖曳产生的空位簇，可以很容易地退火，只留下位错相关的深能级。巢穴.
Three SiGe∕Si heterostructures with different Ge contents have been examined by deep level transient spectroscopy (DLTS) and capacitance-voltage techniques. DLTS revealed a broad band of traps from 80to250K in the as-grown samples. Arrhenius plots of a 25% SiGe sample revealed three trap levels at 0.28, 0.31, and 0.43eV above the valance band, respectively. By varying the reverse biases and comparing samples of different Ge contents, it was found that the trap levels shift toward the valance band with increasing Ge concentration. Capacitance-voltage data indicated that the acceptor trap levels in the SiGe graded layer dramatically decreased from 40×1013cm−3 in the as-grown sample to 4×1013cm−3 after annealing at over 800°C. Based on their charge states and thermal annealing behaviors, we suggest that majority of the grown-in acceptor levels are likely due to vacancy clusters generated by dislocation jog dragging, which can be readily annealed out, leaving only the dislocation related deep levels. The dens...