Hardware Implementation of POSITs and Their Application in FPGAs

Hardware Implementation of POSITs and Their Application in FPGAs
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DOI:
10.1109/ipdpsw.2018.00029
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发表时间:
2018-05
期刊:
2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
影响因子:
--
通讯作者:
Artur Podobas;S. Matsuoka
Artur Podobas;S. Matsuoka
中科院分区:
其他
文献类型:
--
作者:
Artur Podobas;S. Matsuoka

文献摘要

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Dennard缩放的失败,摩尔定律的终结以及深度神经网络(DNN)的最新发展正在导致计算机科学家,从业者和供应商从根本上修改计算机架构,以寻找潜在的性能改进。一个这样的候选人是重新评估如何执行浮点运算,这在过去的三十年里保持(几乎)不变。POSIT数值格式于2017年年中推出,据称与IEEE-754相比更准确,具有更宽的动态范围和更少的未使用状态。然而,迁移到POSIT格式的硬件影响是未知的。在本文中,我们提出了我们的研究结果POSITs和他们的现场可编程门阵列(FPGA)的实现。我们设计了一个工具,可以自动生成和管道化POSIT运算符,这些运算符可以在处理单元或高级综合工具(例如,英特尔FPGA SDK for OpenCL)中用作直接替代。我们凭经验量化的性能和面积开销的POSIT实现相比,两个著名的IEEE-754实现,并表明我们的单位可以在可比的频率。最后,我们将展示如何将POSIT硬件集成到现有的英特尔FPGA SDK for OpenCL数据路径中,使软件程序员能够轻松地继续评估POSIT。
The failure of Dennard's scaling, the end of Moore's law and the recent developments regarding Deep Neural Networks (DNN) are leading computer scientists, practitioners and vendors to fundamentally revise computer architecture to look for potential performance improvements. One such candidate is to re-evaluate how floating point operations are performed, which have remained (nearly) unchanged for the past three decades. The POSIT numerical format was introduced in mid-2017 and is claimed to be more accurate, have a wider dynamical range and fewer unused states compared to the IEEE-754. However, the hardware implications of migrating to a POSIT format are unknown. In this paper, we present our results regarding POSITs and their implementation on Field-Programmable Gate-Arrays (FPGAs). We designed a tool that automatically generates and pipelines POSIT operators that can be used as drop-in replacement in processing units or in High-Level Synthesis tools (e.g. Intel FPGA SDK for OpenCL). We empirically quantified the performance and area overhead of our POSIT implementation compared to two well-known IEEE-754 implementations, and show that our units can operate at comparable frequencies. We finally show how we can integrate our POSIT hardware into existing Intel FPGA SDK for OpenCL data-paths, enabling software programmers to easily continue to evaluate POSITs.