Application-specific signatures for transactional memory in soft processors
Application-specific signatures for transactional memory in soft processors
复制标题
软处理器中事务内存的特定于应用程序的签名
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
J. Steffan
中科院分区：
文献类型：
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作者：
Martin Labrecque;M. C. Jeffrey;J. Steffan
由于可重新配置的计算硬件并且特别是基于FPGA的片上系统包括越来越多的处理器和加速器核，因此以可扩展且易于编程的方式支持共享和同步成为挑战。超高速存储器（TM）是解决这一问题的潜在方案，基于FPGA的系统提供了在硬件中支持TM（HTM）的机会。虽然有许多提议的方法来支持ASIC的HTM，但这些方法不一定能很好地映射到FPGA。特别是在这项工作中，我们证明，虽然基于签名的冲突检测方案（基本上是位向量）应该直观地是一个很好的匹配位并行的FPGA，以前的方法导致不可接受的multicomplexer失速，工作频率，或假冲突率。利用基于FPGA的系统的可重构性，我们提出了一个应用程序特定的签名机制HTM冲突检测。我们的评估使用真实的和预计的基于FPGA的软多处理器系统，支持HTM和实现线程，共享内存的网络数据包处理应用程序。我们发现，我们的应用程序特定的方法：（i）保持125 MHz的合理工作频率，（ii）相对于在2线程架构上具有位选择的签名，实现了分组吞吐量的9%至71%的增加，以及（iii）允许我们的HTM实现6%，54%，和57%的数据包吞吐量增加了8线程架构与基线锁为基础的同步的四个数据包处理应用程序的研究，由于减少了假同步。
As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchronization in a way that is scalable and easy to program becomes a challenge. Transactional Memory (TM) is a potential solution to this problem, and an FPGA-based system provides the opportunity to support TM in hardware (HTM). Although there are many proposed approaches to HTM support for ASICs, these do not necessarily map well to FPGAs. In particular in this work we demonstrate that while signature-based conflict detection schemes (essentially bit-vectors) should intuitively be a good match to the bit parallelism of FPGAs, previous approaches result in unacceptable multicycle stalls, operating frequencies, or false-conflict rates. Capitalizing on the reconfigurable nature of FPGA-based systems, we propose an application-specific signature mechanism for HTM conflict detection. Our evaluation uses real and projected FPGA-based soft multiprocessor systems that support HTM and implement threaded, shared-memory network packet processing applications. We find that our application-specific approach: (i) maintains a reasonable operating frequency of 125 MHz, (ii) achieves a 9% to 71% increase in packet throughput relative to signatures with bit selection on a 2-thread architecture, and (iii) allows our HTM to achieve 6%, 54%, and 57% increases in packet throughput on an 8-thread architecture versus a baseline lock-based synchronization for three of four packet processing applications studied, due to reduced false synchronization.