Performance of 70 nm strained-silicon CMOS devices
Performance of 70 nm strained-silicon CMOS devices
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70 nm 应变硅 CMOS 器件的性能
DOI：
10.1109/vlsit.2003.1221107
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发表时间：
2003
期刊：
影响因子：
--
通讯作者：
F. Wen
中科院分区：
文献类型：
--
作者：
J. Hwang;J. Ho;S. Ting;T. Chen;Y. S. Hsieh;C. Huang;Y. Chiang;H.K. Lee;A. Liu;T. Shen;G. Braithwaite;M. Currie;N. Gerrish;R. Hammond;Anthony Lochtefeld;F. Singaporewala;M. Bulsara;Q. Xiang;M. Lin;W. Shiau;Y. Loh;J.K. Chen;S. Chien;F. Wen
一个86%的电子迁移率的改善和超过20%的I/sub dn-sat/增强被证明为70 nm应变硅CMOS工艺上SiGe虚拟衬底上制造。与体硅CMOS工艺相比，应变硅工艺提供了95%以上的反相器峰值电流和2.2 ps的环形振荡器延迟减少相同的驱动电流。应变和体CMOS功能等效栅极泄漏通过16 /spl的Aring/氮化氧化物，这仍然是主要的泄漏源，尽管观察到的位错引起的应变硅晶片上的结泄漏。应变硅CMOS由于低热导率SiGe虚拟衬底的自加热在DC操作期间将I/sub dn-sat/减小7%。
An 86% electron mobility improvement and over 20% I/sub dn-sat/ enhancement were demonstrated for a 70 nm strained-Si CMOS process fabricated on SiGe virtual substrates. Compared to a bulk-Si CMOS process, the strained-Si process delivered 95% higher inverter peak-current and a 2.2 ps reduction in ring oscillator delay for the same drive current. Strained and bulk CMOS featured equivalent gate leakage through a 16 /spl Aring/ nitrided oxide, which remained the dominant leakage source despite dislocation-induced junction leakage observed on strained-Si wafers. Self-heating of strained-Si CMOS due to the low thermal conductivity SiGe virtual substrate reduces I/sub dn-sat/ by 7% during DC operation.