A Realization of Multiple-Output Functions by a Look-Up Table Ring
A Realization of Multiple-Output Functions by a Look-Up Table Ring
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发表时间：
2004-12
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通讯作者：
H. Qin;Tsutomu Sasao;M. Matsuura;Shinobu Nagayama;Kazuyuki Nakamura;Y. Iguchi
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作者：
H. Qin;Tsutomu Sasao;M. Matsuura;Shinobu Nagayama;Kazuyuki Nakamura;Y. Iguchi
查找表（LUT）级联是一种新型的可编程逻辑器件（PLD），它提供了实现多输出功能的替代方法。 LUT 环是 LUT 级联的模拟器。与LUT级联相比，LUT环更加灵活。在本文中，我们讨论使用LUT环实现多输出功能。与逻辑功能的 FPGA 实现不同，LUT 环实现中可以轻松准确预测延迟时间。 LUT 环原型采用 0.35 μm CMOS 技术定制设计。仿真结果表明，当LUT环和MPU的频率相同时，LUT环比SH-1上的软件程序快80至241倍，比PenliumIII上的软件程序快36至93倍，但比商用FPGA稍慢。
A look-up table (LUT) cascade is a new type of a programmable logic device (PLD) that provides an alternative way to realize multiple-output functions. An LUT ring is an emulator for an LUT cascade. Compared with an LUT cascade, the LUT ring is more flexible. In this paper we discuss the realization of multiple-output functions with the LUT ring. Unlike an FPGA realization of a logic function, accurate prediction of the delay time is easy in an LUT ring realization. A prototype of an LUT ring has been custom-designed with 0.35 μm CMOS technology. Simulation results show that the LUT ring is 80 to 241 times faster than software programs on an SH- 1, and 36 to 93 times faster than software programs on a PenliumIII when the frequencies for the LUT ring and the MPUs are the same, but is slightly slower than commercial FPGAs.