SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices
SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices
复制标题
DOI：
10.1038/s41598-020-59121-0
复制
发表时间：
2020-02-13
影响因子：
4.6
通讯作者：
Suri, Manan
中科院分区：
文献类型：
--
作者：
Kingra, Sandeep Kaur;Parmar, Vivek;Suri, Manan
基于冯·诺伊曼架构的计算机将计算和存储隔离开来（即数据在计算块（处理器）和内存块之间穿梭）。数据的来回移动导致了现代计算机的一个基本限制，即所谓的“内存墙”。内存逻辑(LIM)/内存计算（IMC）方法旨在通过直接在内存单元内进行计算来解决这一瓶颈，从而消除了能源密集型和耗时的数据移动。在最近的一些文献中，提出直接使用新兴的电阻存储器件阵列（例如-忆阻器，RRAM/ReRAM， PCM， CBRAM, OxRAM， STT-MRAM等）来实现逻辑功能，而不是使用传统的晶体管进行计算。数字系统的逻辑/嵌入式端（如处理器、微控制器）可以极大地受益于这种LIM实现。然而，数字系统的纯存储端（例如ssd、企业存储等）不会从这种LIM方法中获得太多好处，因为当内存阵列用于逻辑时，它们失去了存储的核心功能。因此，需要一种方法来补充现有的LIM技术，这对数字系统的存储端更有利；一种为存储器阵列提供计算能力而不以其现有存储状态为代价的方法。从根本上说，这需要能够同时存储和计算的存储纳米器件阵列。在本文中，我们提出了一种新的“内存中同步逻辑”（SLIM）方法，这是对文献中现有LIM方法的补充。通过广泛的实验，我们展示了新型SLIM位单元（1T-1R/2T-1R），包括非丝状双层模拟OxRAM器件和NMOS晶体管。所提出的位单元能够同时实现内存和逻辑操作。给出了详细的编程方案、阵列级实现和控制器结构。此外，为了研究SLIM方法对现实世界实现的影响，我们对两种应用进行了分析：(i) Sobel边缘检测，（ii）二元神经网络-多层感知器（BNN-MLP）。通过在SLIM位单元阵列中执行所有计算，与传统计算相比，在边缘检测应用中，SLIM位单元节省了大约75倍的能量延迟积（EDP） （2T-1R大约40倍），而在BNN-MLP应用中，SLIM位单元分别节省了大约3.5倍的能量延迟积（EDP） （2T-1R大约1.6倍）。由于减少了CPU内存之间的数据传输，EDP节省大约为780x（对于两个SLIM位单元）。
von Neumann architecture based computers isolate computation and storage (i.e. data is shuttled between computation blocks (processor) and memory blocks). The to-and-fro movement of data leads to a fundamental limitation of modern computers, known as the Memory wall. Logic in-Memory (LIM)/In-Memory Computing (IMC) approaches aim to address this bottleneck by directly computing inside memory units thereby eliminating energy-intensive and time-consuming data movement. Several recent works in literature, propose realization of logic function(s) directly using arrays of emerging resistive memory devices (example- memristors, RRAM/ReRAM, PCM, CBRAM, OxRAM, STT-MRAM etc.), rather than using conventional transistors for computing. The logic/embedded-side of digital systems (like processors, micro-controllers) can greatly benefit from such LIM realizations. However, the pure storage-side of digital systems (example SSDs, enterprise storage etc.) will not benefit much from such LIM approaches as when memory arrays are used for logic they lose their core functionality of storage. Thus, there is the need for an approach complementary to existing LIM techniques, that's more beneficial for the storage-side of digital systems; one that gives compute capability to memory arrays not at the cost of their existing stored states. Fundamentally, this would require memory nanodevice arrays that are capable of storing and computing simultaneously. In this paper, we propose a novel 'Simultaneous Logic in-Memory' (SLIM) methodology which is complementary to existing LIM approaches in literature. Through extensive experiments we demonstrate novel SLIM bitcells (1T-1R/2T-1R) comprising non-filamentary bilayer analog OxRAM devices with NMOS transistors. Proposed bitcells are capable of implementing both Memory and Logic operations simultaneously. Detailed programming scheme, array level implementation, and controller architecture are also proposed. Furthermore, to study the impact of proposed SLIM approach for real-world implementations, we performed analysis for two applications: (i) Sobel Edge Detection, and (ii) Binary Neural Network- Multi layer Perceptron (BNN-MLP). By performing all computations in SLIM bitcell array, huge Energy Delay Product (EDP) savings of approximate to 75x for 1T-1R (approximate to 40x for 2T-1R) SLIM bitcell were observed for edge-detection application while EDP savings of approximate to 3.5x for 1T-1R (approximate to 1.6x for 2T-1R) SLIM bitcell were observed for BNN-MLP application respectively, in comparison to conventional computing. EDP savings owing to reduction in data transfer between CPU memory is observed to be approximate to 780x (for both SLIM bitcells).