A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder
A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder
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DOI：
10.1109/tvlsi.2008.2008456
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发表时间：
2009-06
影响因子：
2.8
通讯作者：
Yuan-Chun Lin;Y. Lin
中科院分区：
文献类型：
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作者：
Yuan-Chun Lin;Y. Lin
提出了一种用于H.264/AVC解码的高性能硬连线去块滤波器。为了解码QFHD（3840倍2160，即4倍全高清）超高清视频，我们尽量减少处理周期、工作频率和外部内存流量。我们提出了一种新的滤波顺序，并采用5级流水线和资源共享的双边缘滤波器，每个周期产生两个滤波结果。利用跳过模式，我们的过滤器在最好的情况下只需要48个周期来过滤宏块，在最坏的情况下只需要100个周期。此外，它通过一种新颖的片内存储器方案消除了大多数不必要的片外存储器流量。我们的设计可以支持QFHD在30 fps应用程序仅运行在98 MHz。
We propose a high-performance hardwired deblocking filter for H.264/AVC decoding. To decode QFHD (3840 times 2160, i.e., four times full HD) ultra high definition video, we minimize number of processing cycles, working frequency and amount of external memory traffic. We propose a novel filtering order and employ a 5-stage pipelined and resource-shared dual-edge filter to generate two filtering results every cycle. Taking advantage of skip modes, our filter takes only 48 cycles to filter a macroblock in the best case and 100 in the worst case. Furthermore, it eliminates most unnecessary off-chip memory traffic with a novel on-chip memory scheme. Our design can support QFHD at 30 fps application by running only at 98 MHz.