In-situ Formation of HfN/HfSiON Gate Stacks with 0.5 nm EquivalentOxide Thicness Utilizing Electron Cyclotron Resonance Plasma Sputtering on Three-Dimensional Si Structures
In-situ Formation of HfN/HfSiON Gate Stacks with 0.5 nm EquivalentOxide Thicness Utilizing Electron Cyclotron Resonance Plasma Sputtering on Three-Dimensional Si Structures
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利用电子回旋共振等离子体溅射在三维 Si 结构上原位形成 0.5 nm 等效氧化物厚度的 HfN/HfSiON 栅堆叠
DOI：
10.1143/jjap.50.04da09
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发表时间：
2011
影响因子：
1.5
通讯作者：
Shun-ichiro Ohmi
中科院分区：
文献类型：
--
作者：
Takahiro Sano;Shun-ichiro Ohmi
采用电子回旋共振（ECR）等离子体溅射法在三维Si结构上原位生长HfN/HfSiON栅叠层。优化了原位形成的HfN/HfSiON的沉积后退火（PDA）条件，以抑制发生在栅堆叠结构的界面处的反应，从而实现小的等效氧化层厚度（EOT）、低的漏电流和低的界面态密度（Dit）。发现600 C/15 s是HfN/HfSiON/p-Si（100）结构的PDA的合适条件，以减小电容-电压（C-V）特性中的Dit和滞后宽度。HfN/HfSiON/p-Si（100）在600 ℃退火后的EOT为0.5nm，Dit为1011 cm-2 eV-1量级。在600 ℃下退火的HfN/HfSiON栅叠层即使在3D Si结构上也具有良好的C-V特性，EOT小至0.53 nm。
In situ formation of HfN/HfSiON gate stacks on three-dimensional (3D) Si structures using electron cyclotron resonance (ECR) plasma sputtering method was investigated. The conditions of postdeposition annealing (PDA) of in situ formed HfN/HfSiON were optimized to suppress reactions occurring at the interfaces of the gate stack structures for realizing a small equivalent oxide thickness (EOT), low leakage current, and a low density of interface state (D it). It was found that 600 C/15 s was a suitable condition of PDA of the HfN/HfSiON/p-Si (100) structure to decrease D it and hysteresis width in the capacitance–voltage (C–V) characteristic. The EOT and D it of HfN/HfSiON/p-Si (100) annealed at 600 C were 0.5 nm and an order of 10 11 cm-2 eV-1, respectively. Furthermore, an excellent C–V characteristic of the HfN/HfSiON gate stack annealed at 600 C was obtained even on 3D Si structures, and the EOT was as small as 0.53 nm.