Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication
Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication
复制标题
全流水线的能源效率：矩阵乘法的案例研究
DOI：
--
复制
发表时间：
2016
期刊：
影响因子：
--
通讯作者：
A. DeHon
中科院分区：
文献类型：
--
作者：
Peipei Zhou;Hyunseok Park;Zhenman Fang;J. Cong;A. DeHon
定制的流水线设计可最小化流水线启动间隔（II），从而使采用高级综合（HLS）设计的FPGA加速器的吞吐量最大化。最小化II对能效有何影响？通过一个矩阵乘法加速器，我们表明，由于节省了互连，II>1的矩阵乘法有时可将动态能耗降低到低于II = 1的水平，但II = 1总能使能耗接近最小值。我们还确定了商业工具流程中低效映射的来源。
Customized pipeline designs that minimize the pipeline initiation interval (II) maximize the throughput of FPGA accelerators designed with high-level synthesis (HLS). What is the impact of minimizing II on energy efficiency? Using a matrix-multiply accelerator, we show that matrix multiplies with II>1 can sometimes reduce dynamic energy below II=1 due to interconnect savings, but II=1 always achieves energy close to the minimum. We also identify sources of inefficient mapping in the commercial tool flow.