Analysis of trap generation during programming/erasing cycling in silicon nanocrystal memory devices
Analysis of trap generation during programming/erasing cycling in silicon nanocrystal memory devices
复制标题
DOI：
10.1088/0268-1242/26/4/045011
复制
发表时间：
2011-04
影响因子：
1.9
通讯作者：
Xiaonan Yang;Yong Wang;M. Zhan;Z. Huo;Qin Wang;S. Long;Ming Liu
中科院分区：
文献类型：
--
作者：
Xiaonan Yang;Yong Wang;M. Zhan;Z. Huo;Qin Wang;S. Long;Ming Liu
使用电容-电压和电流-电压测量的组合来分析 Fowler-Nordheim 编程/擦除 (P/E) 循环期间非易失性硅纳米晶体存储器的陷阱生成。随着P/E循环次数的增加，由于积累中的空穴俘获，平带电压降低；由于反转中的电子俘获，阈值电压增加。空穴和电子俘获的产生分别通过阳极空穴注入机制和阴极注入机制来解释。研究发现，空穴和电子俘获的大小取决于 Fowler-Nordheim 编程和擦除偏置条件。将栅极电压从强积累扫描到强反转，在循环器件中，栅极电流尖峰出现在硅中能带电压附近，这归因于隧道氧化物中的俘获空穴与来自本征费米能级之上的受主界面态的隧道电子之间的复合。
Trap generation of a nonvolatile silicon-nanocrystal memory during Fowler–Nordheim programming/erasing (P/E) cycling is analyzed using the combination of capacitance–voltage and current–voltage measurements. With increasing the number of P/E cycles, the flatband voltage decreases due to hole trapping in the accumulation; the threshold voltage increases due to electron trapping in the inversion. The generation of hole and electron trapping is explained by an anode hole injection mechanism and a cathode injection mechanism, respectively. It is found that the magnitudes of hole and electron trapping depend on both Fowler–Nordheim programming and erasing bias conditions. Sweeping gate voltage from strong accumulation to strong inversion, a gate current spike appears near the silicon midgap voltage in cycled devices and is attributed to the recombination between trapped holes in the tunneling oxide and tunneling electrons from the acceptor interface states above the intrinsic Fermi level.